Home > 45nm, 65nm, 90nm, Cadence, CDNLive, DFM, EDA, IDM, Michael J. Fister, SoC > Growth drivers for semiconductor industry

Growth drivers for semiconductor industry

October 19, 2007

Michael J. Fister, president and CEO, Cadence Design Systems Inc., who was in India for the CDNLive event, delivered a wonderful keynote at the recently held CDNLive. Here’s what he had to say!

The semiconductor industry is maturing. Since 2000, the industry’s annual growth rate has experienced extreme highs and lows.

Though the semiconductor industry’s revenue growth will be low in 2007, the good news is that growth rates are smoothing out as costly fabs demand consistent production. Wireless communications, computers, and consumer products continue to be the growth drivers for semiconductors. A couple of the semiconductor technology trends driving electronic design and product development are:

* More designs at advanced nodes — Beginning this year, 90nm designs will outnumber those at 130nm. Meanwhile, 65nm is design activity is ramping up and advanced designs are targeting 45nm.

* Growth in transistor count and logic — Not only are transistor counts increasing according to Moore’s Law, those transistors are being used to create more functions -– and therefore more complexity -– on a single chip, not just adding memory to the existing designs.

A related trend is that the amount of chip production outsourced to foundries continues to grow, with many Integrated Device Manufacturers (IDMs) moving to a ‘Fab-lite’ strategy for advanced nodes. This is happening as design is becoming a greater product differentiation than production.

Note that Fister’s reference to Fab-lite is interesting, even though lot of new investments are said to be getting into, and he himself says, “costly fabs demand consistent production.” There is another point that should not be overlooked — the one concerning Qualcomm, a fabless company, making it to the Top 10 semicon companies, for the first time.

Coming back the Cadence CEO, all of these trends create two kinds of challenges for chip design. These are: 1) manufacturability at advanced process nodes like 90nm and below, and 2) increased complexity and scale of chip design of system-on-chip (SoC).

Design solutions today must address these challenges, and increase team productivity and schedule predictability. To accomplish this, Cadence is focused on a holistic approach to the design flow. The Cadence Low-Power Solution and the Encounter Timing System are good examples of this holistic approach addressing the challenges of escalating scale and complexity.

The same holistic approach is shown in Cadence’s approach to manufacturability, which is to integrate design for manufacturability (DFM) into all aspects of the design flow, rather than just apply DFM techniques as a post-design step.

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Categories: 45nm, 65nm, 90nm, Cadence, CDNLive, DFM, EDA, IDM, Michael J. Fister, SoC Tags: , ,
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