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Importance of power awareness in chip designing

December 15, 2007

Power awareness is said to be crucial for portable applications. It determines the battery lifetime, and there’s an increased amount of computation involved as well.

The other factor is that power awareness is extremely crucial for high-performance applications. This determines cooling and energy costs as well. Many chip designs today are power limited and still require maximum performance.

Battery storage has been a limiting factor as well. The reasons are manifold. For one, battery energy doubles in a decade! It does not follow Moore’s law! Next, there has been little change in the basic battery technology. A battery stores energy using a chemical reaction. Hence, the energy density/size safe handling are limiting factors as well for batteries.

Low power challenges in VLSI domain
There are low power challenges in the VLSI domain. The challenge is four-fold in nature. The devices are leaky. Further, more integration means more W/cm2, while the EDA tools used are not that good in the low-power domain and also doesn’t co-relate sometimes with the silicon. Finally, the variability of the device parameters simply make things worse.

Power dissipation is of two types — static and dynamic. Static power dissipation can be minimized by reducing the operating voltage and using fewer leaking transistors. Dynamic power dissipation can be minimized by reducing the operating voltage, and by less switching capacity, and less switching activity.

Several leakage mitigation techniques are currently in use, such as lower operating voltage, cell sizing, dual Vt, power gating, non-minimum size gate lengths, VTCMOS and stack effect.

According to Jayanta Lahiri, director, PIPD, ARM, the company uses two methods — IEM and PMK.

ARM Artisan power management kit uses power gate components, which can switch between ‘global’ and local rail. It makes use of VDD Header and VSS Footer switches, and high-Vt switch for low off-current leakage. It also uses coarse-grain power gates for multiple cells, which are available in different sizes.

Another ARM Artisan power management kit uses state retention components. The ‘global’ power rails to retention latch. It has power-switched primary master/slave latches, and high-Vt switch for low off-current leakage. It also makes use of the single-pin retention control (RETN), which can save the state on falling-edge of RETN and also restore state on rising-edge of RETN.

Power gated memory facilitates the standby mode, the retention mode and the shutdown mode. In the standby mode (HALT), the CEN disables the memory and leakage only standby current.

In the retention mode (SRPG), power is supplied to the core array to retain state. Power is off for periphery for reduced leakage and the outputs are clamped to zero.

In the shutdown mode (OFF), power is off for the core and periphery for reduced leakage, and the outputs are clamped to zero.

This is possible through both integrated MTCMOS power-gates as well as separated power sources for the core and periphery.

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