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Power awareness critical for chip designers

January 14, 2008

The holy grail of electronics — low-power design, or having the requisite power awareness is extremely critical for chip designers working on both high-performance applications and portable applications. For one, it determines the battery lifetime of a device, besides determining the cooling and energy costs. It is said that several of today’s chip designs are limited in terms of power and still require maximum performance.

Touching on the global factors, S.N. Padmanabhan, Senior Vice President, Mindtree Consulting, said the Kyoto Protocol mandates energy conservation efforts.

Low-power design challenges
Asia, as we all know, has been emerging as a major energy consuming society. Shortage of electricity is becoming a major concern. There is a huge strain on nations to meet the rising needs/halt rise. There is also a rapid increase in all types of electronic goods in growing economies. As a result, increased efficiencies and reduced consumption should be beneficial as a whole!

In the Indian context, the country has around 125 million televisions sets, 5 million automatic washing machines, 10 million white goods, 200+ million other electronics, over 90 million cell phones and 50 million land lines, etc. A 1W reduction in white goods and TVs would lead to a saving of 140 Mi Watts of power! And, a 10 mW reduction in phones will save 1.4 Mi Watts!! Therefore, it makes even more sense to go low power!

Mindtree’s Padmanabhan said IC power budgets have come down drastically. It is <2W for four out of five chips designed. There has also been a simultaneous manipulation of multiple parameters (P=CV2f). Next, there are several leakage issues in 65nm and smaller geometries, which can no longer be ignored.

Add to all of these are factors that there is a lack of availability of comprehensive tools and techniques, as well as analog designs. In such a scenario, designers need to be very clear about their objectives — is it achieving lowering average power, lowering the maximum peak power or lowering energy.

Jayanta Kumar Lahiri, Director, ARM, pointed out challenges associated with batteries. Battery storage has been a limiting factor. Battery energy doubles in a decade and surely, does not follow the Moore’s law. Next, there have hardly been major changes in the basic battery technology. The energy density/size safe handling are limiting factors as well for batteries.

He added that the low-power challenge is four-fold in the VLSI domain. These are — leakiness; more integration means more W/cm^2; EDA tools not that good in low power domain and does not co-relate sometimes with the silicon, and variability of device parameters make things worse.

Toshiyuki Saito, Senior Manager, Design Engineering Division NEC Electronics Japan, said low power is necessary for customer’s success — in form of heat suppress for wired systems and improved battery life time for mobile systems. It also brings cost competitiveness for SoC suppliers in terms of packaging cost, and development cost and turnaround time. Finally, it would contribute to preserving the global environment.

Addressing low power challenges
What are semiconductor and EDA companies doing to address the low-power design challenges? Padmanabhan said several techniques were being employed at the circuit level. However, each one of those had limitations.

These include AVS — which provides maximum savings, reduces speed, but may need compensation; clock gating — which does not help to reduce leakage and needs additional gates; and adaptive clock scaling — which needs sophistication and is not very simple; and finally, the use of multi threshold cells for selective trade-off.

Emerging techniques include efficient RTL synthesis techniques, which is fast, but leaky, vs. slow and low power; power aware resource sharing, which is planning to be done at the architectural level and synthesis, but is not as widely used as other techniques; and power gating methodology — which makes use of sleep transistors, has coarse and fine grained methods, reduces dynamic and leakage power, and also exploits idle times of the circuit.

He added that power optimization should start at the architecture and design stages. Maximum optimization can be achieved at the system level. Also, the evolving power optimization tools and methodologies required collaborative approaches.

Power Forward Initiative
Pankaj Mayor, Group Director, Industry Alliances, Cadence Design Systems, said low power imperative is driving the semiconductor and EDA industries. He said, “design-based low power solution is the only answer!” Traditional design-based solutions are fragmented. Basic low power design techniques, such as area optimization, multi-Vt optimization and clock gating were automated in the 1990s.

There has since been an impact of advanced low-power techniques. These advanced techniques include multi-supply voltage (MSV), power shut-off (PSO), dynamic and adaptive voltage frequency scaling (DVFS and AVS), and substrate biasing. Cadence’s low-power solution uses advanced techniques.

According to Mayor, the Power Forward Initiative (PFI) has created an ecosystem as well. The Power Forward Initiative includes Cadence and 23 other companies across the design chain, as of the end of December 2007.

The year 2007 also saw a continued Power Forward industry momentum. In Q1-07, Common Power Format or CPF became the Si2 [Silicon Integration Initiative] standard. The Cadence Low Power Solution production released V 1.0 in this quarter as well. In H2-07, the industry has seen over 100 customers adopting CPF-based advanced low power solution as well as ~50 tapeouts.

CPF allows holistic automation and validation at every design step. Arijit Dutta, Manager, Design Methodology, Freescale Semiconductor exhibited the advantages of using the CPF in wireless, networking and automotive verticals at Freescale.

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