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Encouraging developments in 22nm!

April 25, 2008

Suddenly, but steadily, there seems to be lot of work going on in the 22nm space. This can only be encouraging for the global semiconductor industry.

Savor these! This week, SEMATECH researchers presented trend-setting research results in extending the CMOS logic and memory technologies at the International Symposium on VLSI Technology, System and Applications (VLSI-TSA), which ran from April 21-23, at Hsinchu, Taiwan.

According to SEMATECH, the new materials, processes and concepts discussed in a series of seven research papers describe how current semiconductor technologies can benefit from performance-enhancing features for future scaling needs.

The papers discuss leading-edge research into areas such as high-k/metal gate (HKMG) materials, flash memory, planar and non-planar CMOS technologies, including new finFET designs, which offer additional control on the channel or body of the device by using a controlling gate wrapped around a thin silicon “fin”.

Early this month, Chartered Semiconductor Manufacturing, one of the world’s top dedicated foundries, announced the extension of its joint development collaboration with IBM to include 22nm bulk complementary metal oxide semiconductor (CMOS) technology.

IBM and AMD have also been collaborating on the development of next-generation semiconductor manufacturing technologies since January 2003. In November 2005, the two firms announced an extension of their joint development efforts until 2011, covering 32nm and 22nm process technology generations. Intel has been working on 22nm for quite some time now.

And last July, PULLNANO, a project sponsored by the European Commission within the 6th Framework Program (FP6), reported several important results related to the future-generation 32nm and 22nm CMOS technology platforms, including the realization of a functional CMOS SRAM demonstrator built using 32nm design rules.

PULLNANO also proposed an innovative new architecture that could provide even higher performance at 32nm and 22nm, using the so-called ‘air gap’ technique.

Late last year, I attended a Semiconductor International Webcast, where one of the analysts, Carl Johnson of Research Infrastructure, had said that lot of consolidation was happening within the fab space. Mid-level players are consolidating. The customer base is clearly narrowing.

He said: “The cost of designing some of these leading-edge devices, and getting them to market, and then following it up with another product, if you don’t want to be a one-product guy, is a real challenge. That is limiting the number of players that are going into the mega fabs. So, the field is narrowing in 65nm, and 45nm, and as we get to below 45nm, the field is going to get much, much narrower.”

Perhaps, there will be fewer players after all, in the 22nm space. However, all of the encouraging developments mentioned above augur well for the semiconductor industry.

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