EDA as DNA of growth

June 18, 2008

The EDA industry today is abuzz with the proposed takeover bid by Cadence Design Systems for Mentor Graphics, and the reported rejection of that bid by Mentor.

This is a consolidation within the EDA industry waiting to happen. My gut feeling is that it will happen, though it may take some more time.

Those in the semiconductor space are well aware of the role EDA plays as far as chip designing is concerned. With India’s growing might in semiconductors, the EDA companies in India are witnessing consumption rising than ever before.

I recently happened to get into a discussion with Rahul Arya, Marketing Director, Cadence Design Systems (I) Pvt. Ltd, on how the industry has been performing, and how are the EDA companies addressing the design challenges, a few days before the Cadence-Mentor story surfaced.

Following the semiconductor industry trends, the consumption of EDA technologies is growing in regions outside of the US and Europe. According to Arya, the size of the EDA market worldwide is estimated to be about US $5 billion today.

The top three EDA companies — Cadence, Mentor and Synopsys — command three-quarters share of the entire EDA market worldwide. Imagine, what it would do to the EDA industry and to Cadence, if Cadence were to take over Mentor!

EDA in India
Coming to the status of the EDA industry in India, it is a pretty good reflection of what’s happening worldwide. The industry in India is growing and it is healthy. As per the ISA F&S Report 2005, the EDA market in India was estimated at US$110m.

The reasons for this growth are multiple. For instance, Cadence’s customers are growing and hence, so is Cadence. “With all of the major semiconductor MNCs having expanded their footprints by setting up India design centers, more EDA software is getting consumed in India. Indian design services are also growing. Also, some startups are coming up, like Cosmic Circuits, Sankalp, etc., and they are gaining momentum,” added Arya.

So how exactly are the EDA companies addressing 45nm (and 32nm) design challenges? If you look at the work being done in India, it is now pretty cutting edge, and very comparable to the rest of the world.

Arya added: “Our customers are looking for the 3Cs — complexity, cost and convergence. The end users are asking for more features. For example, in their mobile or any other electronic device, which is driving our customers to pack in more functionality on the chips.

“Our customers have multiple challenges at 45nm and below, notably low power, analog-mixed signal and Design for Manufacturing (DFM).”

Challenges in 45nm and below
And what are those? As the industry pushes toward smaller process geometries, the existing design infrastructure must be upgraded holistically to automate power-lowering design techniques. Most power-control methods in use today are manual and implemented ad hoc, leading to an increased risk and cost.

Across the design and manufacturing chain, an urgent need has emerged for an automated, power-aware design infrastructure. To facilitate and support a new era of low-power design innovation, Cadence has formed the Power Forward Initiative (PFI).

Drawing from the collective expertise of leading technology companies, the Power Forward Initiative will create a more systematic, integrated approach to low-power design, providing a platform for higher-level exploration and IP re-use.

The PFI members are already at work on validating the Common Power Format (CPF), a new open specification language that captures all power-specific design, constraint, and functionality requirements, such as multi-supply voltage and power shutoff, in a single file.

Arya noted: “By linking design, verification, and implementation domains, the Common Power Format enables automation of power-reduction techniques and increases predictability. No longer constrained by the risk of low yield or costly re-spins, design teams can focus their time and resources on what matters most —- innovation. Achieving both functional and structural verification before incurring manufacturing costs, and with greater time-to-market opportunities, companies across the design and manufacturing chain can adopt new process geometries and start low-power design projects profitably.

On the subject of DFM, EDA companies are trying their utmost to improve yield. Cadence is trying to bring lot of analysis early in the cycle. The designer has more visibility on those effects, before they get manufactured. It has a host of technology offerings to enable the designers make early decisions.

For example, Cadence has recently worked with TSMC on 9.0 reference flow. It has also worked with ARM on a low-power methodology. The idea is that an industry-wide collaboration will ensure that EDA companies like Cadence are able to provide value to customers.

As customers grapple with technology and time-to-market challenges, the EDA industry will be the DNA of growth.

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