Home > CPLD, FPGAs, Jordan Plofsky, low-power design, LTE, NFC, PLD, WiMAX > Altera strategy to partner with Indian design services firms

Altera strategy to partner with Indian design services firms

December 7, 2008

Turning my attention to the programmable logic market, I took advantage of my recent meeting with Jordan Plofsky, Senior Vice President Market, Altera Corp., during the Altera SOPC conference.

Programmable logic consumption in India has been estimated at between $20-$25 million in 2008, largely driven by strong growth in communications infrastructure and increased spending in the military sector. The Indian programmable logic market is likely to grow at a CAGR of 25 percent over the next three years.

Altera’s India strategy
In this context, it will be interesting to note Altera’s strategy within the Indian semiconductor industry.

Plofsky says that as multinational companies are transferring more design work to their R&D teams in India, local companies are expanding their range of products, and independent design service companies are capturing a bigger piece of the outsourced design pie, Altera forecasts the increased need for high quality application support.

He says: “Unlike other companies who have design services operations in India, which compete with the local independent design services, our strategy is to partner with the local India design services industry. We are expanding our direct and indirect support channels to provide higher quality services to our customers here.”

Altera is also supporting the development of the education sector in India, which is modernizing to turn out well trained engineers to satisfy the appetite of the industry. “We also run industrial workshops and seminars, like the recent SOPC World in Bangalore and New Delhi, to educate the design community on the direction of semiconductor technology,” adds Plofsky.

Altera has also set up Altera Joint Laboratories in leading universities across India to provide a better platform for undergraduates to grasp basics of programmability.

Role in solar?
With investments in solar/PV happening, is there a role for Altera and other FPGA companies? This is a question that I invariably ask everyone in the semiconductor industry!

According to Plofsky, one of the promising applications is smart metering. It is the practice of getting the users and the infrastructure to be power aware and then using different usage patterns to lower energy usage and energy costs by applying smart algorithms.

Addressing low-power design
Power consumption has always been a big concern for designers in all markets and Altera has a number of different solutions.

In the CPLD area, Altera announced its zero power MAX IIZ devices in late 2007. Offering the highest density and I/O count in packages as small as 5x5mm, compared to macrocell-based CPLDs, MAX IIZ devices allow designers to meet changing functional requirements and lower power while saving board space.

Consuming 75 percent less power than competing FPGAs, the Altera Cyclone III devices are the industry’s first and only 65-nm low-cost FPGA family, and offer digital system designers an unprecedented combination of density, power and cost.

To address the low-power demands of high density customers, the Stratix III and Stratix IV family members feature Altera’s patented Programmable Power Technology. This power-saving technology optimizes logic, DSP and memory blocks to maximize performance where needed while delivering the lowest power elsewhere in the design. And in addition these designs can be converted to HardCopy ASIC devices that can reduce power consumption by 50-70 percent.

As for new products in the LTE, TD-SCDMA and NFC spaces, Plofsky says that with the new 40-nm devices, Altera is uniquely positioned to deliver solutions that provide the density, performance and power for these emerging applications. The combination of DSP blocks, memory and transceivers was optimized for these communication applications.

Roadmap beyond
Altera just announced its 40nm devices in May and it is said to be on target to deliver those devices by the end of 2008.

Adds Plofsky: “We have already started development work on smaller process geometries with test chips in fab now, but it is too early to go into any family detail at this time.”

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