Home > chip designers, CustomSim, DFT, Discovery 2009, EDA, EDA tools, Manoj Gandhi, semconductors, Synopsys, VCS2009, verification > Synopsys on Discovery 2009, VCS2009 and CustomSIM

Synopsys on Discovery 2009, VCS2009 and CustomSIM

April 8, 2009

If you’ve been following the EDA industry closely, you’d be well aware of three major announcements by Synopsys over the last couple of days. These are:

* Synopsys introduced the Discovery 2009 verification platform, delivering faster, unified verification solutions.
* It unveiled the VCS multicore technology, delivering 2x verification speed-up.
* It introduced the CustomSim Unified Circuit Simulation solution, which addresses custom digital, analog and memory verification challenges.

I met up with Dr. Pradip K. Dutta, Corporate Vice President & Managing Director, Synopsys (India) Pvt Ltd and Manoj Gandhi, vice president and general manager, verification group @ Synopsys, in an attempt to understand how significant these announcements are for verification.

Verification is huge!
According to Manoj Gandhi, at the macro level, design complexities continue to grow. As this grows, one big challenge is verification. The reason is: today’s SoC designs and large IC designs, they are being approached like large software projects.

He said: “Verification becomes huge, like software. It is expensive in hardware design. We focus on the verification challenges. We introduced the System Verilog about four to five years ago, and we had also acquired ArchPro. Yesterday, we announced the Discovery 2009, CustomSim and VCS2009.”

How can users make use of new CPUs coming out? “We aim to get higher much performance using multicore architecture,” he added.

Introducing VCS2009
The VCS2009 is multicore enabled, runs the industry’s first low-power verification methodology, and enables fastest mixed-signal simulation with the CustomSIM. Focusing on the VCS2009, Gandhi said: “In verification, there’s a design under test and verification. A lot of designs now have multicores. AMD is among the many folks using the VCS2009. Almost every CPU is designed using VCS. It plays a big role in large SoCs.”

Design companies have several activities such as test bench, debug, etc. All of these can now be parallelized. “Customer designs can be simulated on multiple threads,” Gandhi said. “Also, the applications can also be simulated on different threads, called application level parallelism. We can actually bring about 5-7X improvement in verification with the VCS2009.”

According to him, this product is already being used by some large customers. “This is our next phase of performance innovation. The processor roadmap is getting more and more multicore. We have over 200 customers,” he added.

The VCS distributes time consuming activities across multiple cores. Gandhi added that each core has a lot of computations. You may do lot of parallel activities with the mobile phones. All activities are now in parallel.

And how about the speed-up from parallel computation with the industry-leading Native Testbench (NTB)? He said: “We were one of the first to introduce all technologies as part of a single compiler. That brought the 5X speed-up. We did all of this in verification, and a test bench core was brought into verification.”

The combination of DLP and ALP optimizes VCS performance over multicore CPUs. Design level parallelism (DLP) and application level parallelism (ALP) — all CPUs can be threaded on different cores.

Low-power verification methodology published
Synopsys has published a book on industry’s first low-power verification methodology, along with ARM and Renasas. It is an attempt to bring technology to the mainstream — how to do low-power verification. There are other 30 companies who participated in this exercise.

On the CPF vs. UPF debate, he said that UPF is a standard where Magma, Mentor, Synopsys, etc. have participated. Cadence has CPF. Users can make use of this book and apply, on top of both UPF and CPF.

Introducing Discovery 2009
According to Synopsys, this solution is doing very well in the market. The company has seen strong technology leadership over the last two to three years. It has also created strong investments.

CustomSIM is a unified circuit simulation solution. “We have a software to silicon verification focus. We are all the way from system level design to RTL, to software verification, etc. Discovery has some technologies as part of that, noted Gandhi.

What has Synopsys done right?
A most interesting point in the EDA industry, I feel, has been the performance of Synopsys, in an otherwise difficult segment over the past year. So, what are the reasons behind this success?

Gandhi added: “Our management are all strong technologists. We have invested tremendously in bringing in strong technology leaders. In India, many companies needed R&D collaborations locally. For us, it was a big win when we invested in Bangalore. We work closely with customers delivering technologies that will address challenges two-three years from now.

Dr. Pradip Dutta elaborated: “Synopsys is very strong in product leadership (PL). The other two key areas are customer intimacy (CI) and operational excellence (OE). You need to be highest in PL. We have been very conservative even during strong times.”

That is indeed a marvellous thought! Those who are typically strong in technology, generally go on to develop great intimacy with customers, and all of this starts reflecting on their operations, which are anyway excellent! Here’s a message for those who wish to do well in tough times — strong product leadership, coupled with customer intimacy and well, corresponding operational excellence!

Focus on verification
Now that the focus is quite clearly on verification, how do EVE and the other verification companies stand out? EVE is currently in the emulation space. Gandhi added that EVE competes more wtih Cadence and Mentor. “We work with EVE on many accounts. Verification is all about finding bugs. Emulation has been more cyclical.”

According to him, Synopsys is now looking at tackling the next level — how do you reduce the overall cost? “We will go beyond selling tools. We would look at how to identify issues and saving verification costs.” I believe, verification takes up close to 70 percent of an overall design test.

Commenting on the EDA industry in India, both, Dr. Dutta and Gandhi feel it is still buzzing quite well, despite what’s been happening in the global context. “We have invested quite a lot. We have a large team here. We continue to collaborate with local institutions here as well,” Dr. Dutta added.

Advertisements
%d bloggers like this: