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Mentor’s Wally Rhines on EDA industry — II

September 30, 2009 1 comment

Friends, this is a continuation of my conversation with Walden (Wally) C. Rhines, chairman and CEO, Mentor Graphics Corp., who was recently on a visit to India for the EDA Tech Forum as keynoter.

Software-to-silicon verification

Today there’s a growing focus on software-to-silicon verification, encompassing a full range of challenges that also includes embedded software, system validation and integration testing. How true?

Certainly true! The problem of hardware/software codesign and co-verification has been around a long time but, until this decade, generated less than $50million of annual EDA revenue.

Rhines said: “This decade, the market has grown rapidly and companies like Mentor have experience accelerated revenue growth in both their ESL design environments and their embedded software development tools and technology. Emulation has grown increasingly popular to verify not only hardware but to test application/embedded software.

“And, embedded software development tools, technology, RTOS, protocol stacks and LINUX middleware have all become part of the electronic product developers design environment.”

EDA in modeling and photomask correction

How and where does EDA fit into the big picture, particularly in the areas of modeling and photomask correction?

According to Rhines, for photomask correction, the EDA industry is the only provider, with two large EDA companies providing more than 90 percent of the optical proximity correction revenue.

“EDA companies have changed over the last decade due to the growth of OPC and DFM. Wafer fabs have now become major customers. Specialists in optics have joined traditional electronic design specialists at EDA companies to create the key technologies. EDA companies are now leading the way in the development of new process technology as evidenced by the IBM/Mentor joint development program at 22nm, he added. Read more…

Mentor’s Wally Rhines on global EDA industry and challenges

September 24, 2009 1 comment

Walden C. Rhines, chairman and CEO, Mentor Graphics Corp.

Walden C. Rhines, chairman and CEO, Mentor Graphics Corp.

Thanks to Veeresh Shetty at Mentor Graphics, I was very fortunate to get into a conversation with Walden (Wally) C. Rhines, chairman and CEO, Mentor Graphics Corp., who was recently on a visit to India for the EDA Tech Forum as keynoter.

Besides discussing the global EDA industry, the challenges it is currently facing, we also discussed industry issues such as whether the lack of EDA tools is a bottleneck for 3-D implementation, EDA in the big picture, with regard to areas such as modelling and photomask correction, and so on.

State of global EDA industry
According to Walden Rhines, 2008 and the first quarter of 2009 are the weakest periods ever reported by the EDA industry.

He said: “A substantial portion of the weakness during this period was caused by a change in revenue recognition accounting by one of the major EDA companies. Before 2008, there had only been two years of negative EDA revenue growth in history and both of those were very minor negatives (i.e., almost zero) and both of those were caused primarily by changes in revenue recognition accounting, one each by each of two major EDA companies.”

While this recession is the most precipitous drop in electronics industry history, the normal pattern of preserving most R&D spending has been maintained by most electronics companies. As a result, the decline in EDA revenue is small when compared to the decline in semiconductor industry revenue.

“As the electronics industry recovers, and its R&D spending once again comes in line with its growing revenue, the EDA industry should recover as well. Positive signs include the strength of the semiconductor sequential revenue growth in Q209 and the fact that the Q109 rate of year to year decline in EDA revenue was nearly half the rate of decline of the fourth quarter of 2008,” he added.

Tech challenges
What would be the biggest technical challenges facing the EDA industry right now? Rhines said that the largest technical challenges for the EDA industry right now are:

1) low power design (from system level through physical layout),

2) keeping up with the growing functional verification challenge (by developing new approaches including ESL, coverage based verification, emulation, intelligent testbench, hardware acceleration of test benches, assertion-based verification, etc.) and

3) dealing with manufacturing variability (through application of design-for-manufacturing techniques to design).

The conversation continues in a while… I’ll be back!

How Intel manages IT through downturn — Server and data center optimization!

September 15, 2009 Comments off

Ever wondered how Intel is managing IT through the downturn — Server and data center optimization? According to Kenny Sng, data center engineering manager, Intel Technology Asia Pte Ltd, there are three key things that Intel IT does. These are:

• Internal efficiencies are critical in freeing up resources and reducing operational costs.

• Server refresh is a key strategy to ensure IT runs efficiently.

• Intel continues to look at innovation in DC operations for reducing running costs

Server and data center optimization? Intel's Kenny Sng, data center engineering manager, making a point!

Server and data center optimization? Intel's Kenny Sng, data center engineering manager, making a point!

How can IT make a difference?

* Drive employee productivity — by way of mobile client refresh

* Drive business productivity

* Continue IT efficiencies — by way of data center and server refresh

Intel data center profile

Intel has four major groups currently driving individual data center requirements (DOME).

Design:

Support the chip design community

Design Computing: Has most of the servers in Intel

Office:

Supporting typical IT and customer services

General Purpose

Manufacturing:

Manufacturing computing supporting fabrication and assembly

FAB/ATM

Enterprise:

Enterprise applications supporting eBiz and ERP

About 80 percent of servers in Intel are in D. And, 20 percent of servers in Intel are in O, M and E, categories.

Intel IT’s approach to data center optimization

Intel’s approach is very simple — standardize, improve and optimize.

Standardize

* Supply and demand forecasting

* Processes and design specs

* Overall data center structure

All of this  enables IT and consolidations, prevents unnecessary spending and ensures consistency in the overall data center structure.

Improve

* Batch processing pools via grid computing (DCV) – (D)

* Virtualization (DCU) – (O) & (E)

* Replace single core with quad-core servers

* Information Lifecycle Management

* Intel “Green” data center initiatives

* Containerized Data Centers

These go on to reduce server spending and storage/hardware expenses, Contain costs (network, power, space), simplify the environment and well, improve energy efficiency by at least 6x.

Optimize

* Close inefficient and unnecessary data centers

* Assure batch and virtualized servers are in optimal data center locations

What do these do? One, maximize data center utilization in all locations, and two, maximize server asset utilization across the world. Read more…

Cypress on Indian semicon industry trends; launches PSoC 3 and PSoC 5 architectures

September 14, 2009 4 comments

Cypress Semiconductor claims to have revolutionized the embedded design space with its high performance, low power PSoC 3 and PSoC 5 programmable system-on-chip architectures.

Rajeev Mehtani, Senior Vice President, Cypress Semiconductor, India Operations.

Rajeev Mehtani, Senior Vice President, Cypress Semiconductor, India Operations.

Thanks to some great work done by my associate Usha Prasad, and Cypress’ Meghna Bhutoria, I was able to find out more about this launch in an in-depth conversation with Rajeev Mehtani, Senior Vice President, Cypress Semiconductor, India Operations. I also discussed with him, the India advantage for Cypress, as well as his views regarding the Indian semiconductor industry today.

PSoC and its benefits

Cypress’s PSoC is the world’s only programmable embedded SoC integrating configurable analog and digital peripheral functions, memory and a microcontroller on a single chip. It is a revolutionary design methodology.

A number of analog and digital components are available. Then there’s an MCU. Typically, if you take an MCU, everything is fixed. In the PsoC, everything is programmable. ASIC is the end game in full programmability. For PSoC, you can immediately go on with designing the product. You can even make changes as you design. You are not paying for ASIC pricing!

The three main values a PSoC provides customers are:

Integration: The ability to integrate discrete components and reduce BoM costs, reduce manufacturing costs (PCB layout costs), and reduce power consumption with fewer devices.

Programmable Analog: The ability to integrate analog discrete components like amps, filters, ADCs, etc as well as to integrate signal conditioning.

Flexibility: The traditional benefit of programmability—ability to continuously be able to respond to change, real-time and parallel prototype/design/production of products to get to market faster.

PSoC 3 and PSoC 5 architectures

Cypress is introducing new, scalable architectures to extend the PSoC design methodology to the precision analog, programmable digital and high performance 8- to 32-bit world. The PSoC 3 and PSoC 5 architectures consist of numerous product families per architecture with hundreds of devices under each family.

Cypress PSoC

Cypress PSoC

The PSoC 3 and PSoC 5 architectures are powered by high performance, industry-standard processors:

* PSoC 3 architecture is based on a new, high-performance 8-bit 8051 processor with up to 33 MIPS.

* PSoC 5 architecture includes a powerful 32-bit ARM Cortex-M3 processor with up to 100 DMIPS.

Features of the new PSoC 3 and PSoC 5 architectures include: programmable precision analog sub-system, programmable high-performance digital sub-system, high-performance CPU sub-systems, industry leading low power, and programmable and feature-rich I/O and clocking.

PSoC to change way embedded designers solve problems

PSoC removes the barriers designers face with fixed function MCUs. Programmable analog and digital blocks in PSoC give designers the flexibility to adapt to changing requirements quickly and easily, while designing products that specifically meet market demands.

Flexibility

We work in an environment where change is the only constant. PSoC gives designers the flexibility to:

• Add new features to the application.

• Differentiate their products.

• Makes it easy to tune and adjust their designs during debug/system bring-up.

With ASICs and traditional SoC offerings, semiconductor companies around the world offer an assortment of choices — but in the end designers still end up compromising on the system features or on the price they are willing to spend. However, with PSoC, they can optimize, rather than force these compromises and in the end get more functionality, in some cases greater than 100 percent efficiencies, at lower system costs and better power savings, to and get exactly what they need.

Let’s take an example using a typical lifecycle development model. The product marketing group identifies and defines the next big consumer electronic product that’s going to revolutionize the world. Only problem, they’re not exactly sure they fully understand what the requirements are yet but know they need to get moving in order to get the product to market quickly. So, they hand over a set of requirements to the designers who in turn identify what functional components they are going to need to deliver; rough layout, there is some early research and they are usually successfully past the architecture definition milestone in the design lifecycle.

However, as the final architecture design is reviewed and further progress is made through the other phases to get the product into production, marketing continues to clarify the requirements and the developers are expected to quickly adapt those in the design. And this adapting means complete redesigns at every stage of the process. With PSoC, designers have the means to adapt by using the programmable fabric within their device to swap out components, add or remove components and keep the design cycle moving in the right direction—all the way through to production. Read more…

Social computing and sustainability @ Intel

September 11, 2009 Comments off

I Social computing and sustainability @ Intel
I was very fortunate to be part of a discussion around this very theme on which, Dr Liam Keating, Director, APAC SMG IT Operations, Intel, spoke recently in Malaysia.
Intel IT’s operations environment includes 5,700 employess serving 66 IT sites in 28 countries. The team supports 83,000 employees in 150 sites. Intel has 97 data centers, globally. This number should come down further in future.
Intel also has an ~80 percent client mix to mobile, and 6,300 wireless access points. It receives 148 million e-mail messages each month and there’s also over 90 percent adoption of IM. In all, the Intel IT team also manages 18PB of storage capacity, including 989 terabytes backup data per month, as well as over 35 million telephony minutes/month. Quite mind boggling statistics, these!
According to Dr. Keating, environmental pressures are converging on the enterprise. The face of Intel’s IT workforce is also changing, simultaneously. For instance, the a “connected” Gen Y is entering the workforce and demanding new ways to work. Also, knowledge is exiting with the various retiring workers. Another factor is the consumerization of IT. Employees using newer technology at home and demand the same at work.
Intel has a definition of the social enterprise or enterprise social computing: The next generation of online collaborative technologies and practices that people use within the enterprise to share knowledge, expertise, experiences and insight with each other.
It enables iImprovement of sharing, discovery and aggregation of information, helps finding experts fast, expands network and enhances career development, aids in real-time collaboration, helps share innovative ideas, and builds communities.
Enterprise social computing has become the catalyst for business transformation.
The traditional enterprise information workforce was distributed, content repository focused, corporate centered, had individual/small group wisdom, and unknown knowledge. In contrast, the social enterprise 2.0 is aggregated with user generated content, employee centered, transparent, has wisdom of crowds, people are now separated by six degrees, and there’s tacit knowledge.I was very fortunate to be part of a discussion around this very theme on which, Dr Liam Keating, Director, APAC SMG IT Operations, Intel, spoke recently in Malaysia.
I was very fortunate to be part of a discussion around this very theme on which, Dr Liam Keating, Director, APAC SMG IT Operations, Intel, spoke recently in Malaysia.

Intel IT’s operations environment includes 5,700 employess serving 66 IT sites in 28 countries. The team supports 83,000 employees in 150 sites. Intel has 97 data centers, globally. This number should come down further in future.

Intel also has an ~80 percent client mix to mobile, and 6,300 wireless access points. It receives 148 million e-mail messages each month and there’s also over 90 percent adoption of IM. In all, the Intel IT team also manages 18PB of storage capacity, including 989 terabytes backup data per month, as well as over 35 million telephony minutes/month. Quite mind boggling statistics, these!

According to Dr. Keating, environmental pressures are converging on the enterprise. The face of Intel’s IT workforce is also changing, simultaneously. For instance, the a “connected” Gen Y is entering the workforce and demanding new ways to work. Also, knowledge is exiting with the various retiring workers. Another factor is the consumerization of IT. Employees using newer technology at home and demand the same at work.

Enterprise social computing
Intel has a definition of the social enterprise or enterprise social computing: The next generation of online collaborative technologies and practices that people use within the enterprise to share knowledge, expertise, experiences and insight with each other.

It enables improvement of sharing, discovery and aggregation of information, helps finding experts fast, expands network and enhances career development, aids in real-time collaboration, helps share innovative ideas, and builds communities.

Enterprise social computing has become the catalyst for business transformation.

The traditional enterprise information workforce was distributed, content repository focused, corporate centered, had individual/small group wisdom, and unknown knowledge. In contrast, the social enterprise 2.0 is aggregated with user generated content, employee centered, transparent, has wisdom of crowds, people are now separated by six degrees, and there’s tacit knowledge.

Where is the business value?
One may ask: Where is the business value?

The key challenges being addressed by Intel IT include: work more effectively over time and distance; engage the Gen Y worker; connect and engage employees to make Intel feel “small” — tackle feelings of isolation; mitigate impact of a maturing workforce; and improve speed of finding relevant information and people.

The whole idea is to focus on people – and make them more effective at what they do!

The train is coming! So what are the steps to get ahead? These steps include explore-act-nurture.

Explore
– Start using the tools
– Consider the cost of inaction
– What are the silos?

Act
– If IT doesn’t act quickly, somebody else will
– Identify “low-hanging” business value
– Shop for a suite of tools, not disparate solutions
– Integrate tools into business processes
– Conduct security, risk and privacy assessment early
– Document “Terms of Use” policy that align with current code of conduct

Nurture
– Don’t deploy and walk away
– Provide training to facilitate “ways to collaborate” behavior change
– Show “what’s in it for me?”
– Leverage business partnerships

Intel launches Core i7-800 and i5-700 processor series

September 8, 2009 Comments off

Intel has introduced the long-anticipated Intel Core i7-800 and i5-700 processor series.

Today, Tim Bailey, Director of Marketing & Consumer Sales for Intel Asia Pacific and Srinivasan Ramaprasad (Ram), Regional Marketing Manager for Consumer Client Platforms for Intel Asia Pacific presented the Intel Core i7-870 processor, the Intel Core i7-860 processor, the Intel Core i5-750 processor and the Intel Xeon 3400 series.

More details follow in a while.

Dr. Robert Castellano on how to make solar a ‘hot’ sector again – 2

September 7, 2009 2 comments

Friends, this is the concluding part of my conversation with  Dr. Robert N. Castellano, president of  The Information Network, based in New Tripoli, USA.
The question of adding new, additional solar capacity will always arise. Is t certain that no new additional capacity will be brought on board in 2009? Dr. Castellano said: “Actually I said 2010. Solar manufacturers are already losing money this year and the capacity utilization is 27.9 percent. Also, the days of inventory are currently 122, up from 71 days in 2008. If they continue to add new capacity, things will only worsen, exasperating the recession.”
Dr. Robert N. Castellano, president, The Information Network

Dr. Robert N. Castellano, president, The Information Network

Friends, this is the concluding part of my conversation with  Dr. Robert N. Castellano, president of  The Information Network, based in New Tripoli, USA.

The question of adding new, additional solar capacity will always arise. Is it the certain that no new additional capacity will be brought on board in 2009?

Dr. Castellano noted: “Actually I said 2010. Solar manufacturers are already losing money this year and the capacity utilization is 27.9 percent. Also, the days of inventory are currently 122, up from 71 days in 2008. If they continue to add new capacity, things will only worsen, exasperating the recession.”

What lessons for India?
Turning our attention to India, which has lately been witnessing a lot of talks of building new capacity. According to Dr. Castellano, now is a good time to talk, as a plant will take at least a year to get into full production. By that time, prices should be stabilized and increase.

What then are the lessons to learn from all of this for the Indian solar PV industry?

He added: “What has to be weighed is the cost of making the solar panels in India versus buying the outside the country. It can take several years for a plant to be profitable. If the venture was established from money from India’s government through subsidies, it can lessen the impact of potential losses, while the plants ramp and selling prices move up to a level where production becomes profitable.”

I hope this valuable piece of advice is noted by the existing players or those looking to entering the solar photovoltaics segment in India.

Bring solar production cost per watt down
Dr. Castellano had mentioned about First Solar bringing production costs down to $0.93 per watt. How many of the others are capable of matching or bettering this?

He said, for that matter, Oerlikon, expects that its lines will deliver a cost of $0.70 cents per watt by the end of 2010 and has achieved an initial conversion efficiency of 11 percent, which comes out to about 9.5 percent of stabilized efficiency.

How can manufacturers differentiate their solar products?
Another query has been, how should solar manufacturers differentiate their products and how can they do it cheaply?

Certainly, there are new avenues of manufacturing, such as CdTe from First Solar, CIGS from half a dozen manufacturers, multi-junction cells from companies such as Uni-Solar, and building integrated photovoltaics (BIPV) from an increasing number of manufacturers, advised Dr. Castellano.

He said: “These technologies differentiate the companies’ products, but the proportion of wattage manufactured, while growing, is small compared to the majority of solar panels sold using traditional methods of production, i.e., a thin film on a glass substrate.

“Long life and low cost of ownership are of paramount importance if solar is to grow, particularly, if there is to be a large acceptance at the residential level. Manufacturing can introduce defects in solar cells that can result in low electron mobility (EM), electron traps and photo-degradation from UV light. These issues affect the efficiency and lifetime of solar cells and the importance of measuring electron mobility at the wafer and cell stage.

“The lifetime of minority carriers has been widely identified to be the key material parameter determining the conversion efficiency of pn-junctions in silicon solar cells. Defects in the crystal lattice reduce the charge carrier lifetime and thus limit the performance of the solar cells. Another major efficiency loss is due to impurities in the cell. These can be foreign atoms or molecules in the crystal lattice (including the dopant atoms), and provide sites where electrons and holes can recombine, thereby reducing the number of charged particles available to create an electrical current.

“Lehighton Electronics (Lehighton, PA) is an example of a company that has developed a variety of tools to test and measure solar wafers. One tool can measure sheet resistance and resistivity to see if there is any subsurface damage. Another system can measure minority carrier lifetimes, while a third model can find traps in solar wafers.” Read more…

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