Excerpts from Future Horizons’ IEF 2009 — II

November 1, 2009

Presenting excerpts of some more key presentations made on day 1 and 2, resepectively, at the recently held International Electronics Forum 2009 (IEF 2009), in Geneva, Switzerland, from Sept. 30-Oct. 2, which was held under the auspices of the Geneva Chancellerie D’Etat & Istitut Carnot CEA LETI.

May I also take this opportunity to thank Malcolm Penn, chairman and CEO, Future Horizons.

“ICT: Key For Global Competitiveness” — Enrico Villa, chairman, CATRINE

Enrico heads up the Cluster for Application and Technology Research In Europe on NanoElectronics (CATRINE) and through his organisation Europe is preparing for our future with development projects in nanotechnology, microelectronics, photonics, biotechnology and advanced materials.

Electronic and information systems are worth $87 trillion and growing, which is about 10 percent of global GDP. Such systems have penetrated all aspects of life, created millions of jobs and has been a motor of productivity growth.

Microelectronics is a key enabling technology for electronics and ICT, and as a consequence the semiconductor market grows at twice this GDP. The role of electronics will increase in the future and will have an impact in society due to its use in healthcare, aids for an aging population, easing transportation bottlenecks and lowering energy costs.

To meet these targets electronics and ICT must be affordable to the population at large – meaning that semiconductors must meet the trend of doubling performance every two years, reduce price per function by 40 percent per year and aim for R&D nearly 20 percent of sales.

In an example given public lighting is 13 percent of energy costs – a change to semiconductor LEDs can save a third of this energy. Enrico sees moving from ideas to products is one area where Europe is weak, but thankfully projects Jessi/Eureka/Catrine/Medea+ are bringing together cooperation between European players.

This has enabled European companies and universities to work together and create critical masses to make global products. This is born out in the fact that Europe has several global-sized semiconductor companies and two European equipment-material suppliers that are world leaders.

“Raising The Bar On Semiconductor R&D Management, Execution & ROI” — Ronald Collett, CEO, Numetrics Management Systems

Working with the company PRTM Ron is tasked to raise the management competence within the semiconductor industry so companies can compete in the global arena. The semiconductor industry is going through a profound change with the vertically chip companies disintegrating and outsourcing their manufacture. Headcount has fallen, there are fewer start-ups and everybody is cutting costs.

Companies that will survive are those with well differentiated products and superior product development ability. PRTM has produced an integrated framework of product development capabilities, which compares company actual performance against industry best practice and timescales.

It is a fact that 60 percent of semiconductor projects slip in time by at least one quarter and 16 percent slip by more than one year. The system allows ‘fact-based planning and decision making’ and allows management to get no surprise shortfalls in revenue or margin.

At a detailed level, the engineer can make a fact-based project cost estimation and can reliably make staffing requirements and schedules. It allows ‘what-if’ project analyses and calculates risk. The immediate impact is usually a reduction of projects, but a better time-to-market and ROI. An industry shakeout is inevitable and demands will overwhelm all, but the best.

“Building Complex Embedded Software Applications On Leading Edge Silicon” — Martin Orrell, General Manager, Multimedia Technologies, The Technology Partnership

TTP is an independent product development company involved in a wide range of products including embedded systems in medical devices, PC peripherals, MP3 players and automotive, industrial and traffic control.

Martin’s view is that one of the difficulties in embedded design is to recognise that the hardware and software boundaries tend to blur. Using software rather than hardware has its advantages, particularly where the standards and specifications have not firmed up, but software often costs more than the customer planned.

Costs can be saved by the re-use of silicon and software IP, the starting platform and roadmap, trimming the specification and through innovation. TTP has a wide range of experience and can often view a customer project from a different perspective and Martin gave a number of good examples of case studies where this was the case.

To finalise, two tips were given to product developers: More complex software does not mean higher project costs and silicon targeted for a different market can enable innovative opportunities in your own market.

“Lowering The Cost Of SoC Design” — Steve Glaser, Corporate VP Strategic Marketing, Cadence Design Systems

Steve asks: Is it only the rich that can afford IC design?’

Actual and predicted IC design costs have been rising for each process node, but many of these costs have been are due to the cost of failure and delays. Failure is mainly seen in system/software bugs rather than hardware design issues. Delayed product launches are a major issue in 89 percent of projects and many delays are due to ‘changes’ in specification, either due to the market requirement changing or major architectural revisions.

Design productivity must be improved to avoid delays, particularly in the area of verification. Pre-verified IP will make an improvement here particularly if the IP blocks have interfaces that allow fast integration. The number of software code lines has to be reduced as this will decrease development time and reliability (bugs). Software verification has to become automated.

Management is a big issue, particularly in distributed SoC teams, as it is so difficult get a predictable flow of design elements to the backend. Nowadays, many of these issues have been overcome in EDA software. Hardware verification tasks have been cut by a third and computers can handle verification at the SoC level. EDA software and integration-ready IP allows design closure three-four months earlier and modern simulators allow the starting of software coding three-five months earlier. This will not only give first-time working silicon and software, but will achieve time-to-market.

Potential cost savings in the $40M SoC design costs are claimed to be $17M, plus a potential $48M savings on delay-related opportunity ‘costs’ gained on meeting the time-to-market issue!!

“Custom MEMS – Business Models & Successful Differentiation” — Peter Pfluger, CEO, Tronics Microsystems

Tronics is a MEMS foundry spun off from development laboratories LETI. The market is dominated by STMicroelectronics and Texas Instruments, but there are numerous specialist smaller companies many of which are fast growing.

The MEMS market is expected to grow from $6B in 2009 to $12B in 2012. MEMS is a technology for carving 3-D microstructures into silicon to produce mechanical, electromechanical, fluidic, chemical or biomechanical components. MEMS products include miniature accelerometers, inkjet print heads, silicon microphones, pressure sensors, gyroscopes, human drug dispensers, micro fuel cells and gas analysers.

These products have very diverse functionalities, diverse packages and are made on a variety of process technologies. There is, however, a trend towards a generic standard process by making the MEMs on thick SOI, deep etching the components and using an oxide layer to stop the etching. Sandwiches are made with two to four wafers and there is difficulty in making contact through lateral and vertical wafer interconnect.

Peter said volumes of individual MEM products are still low compared to basic ICs and the unit costs are relatively high because of high NREs, test methods, packaging and interfacing (amplifiers must be good), so suppliers find it important to add value by having an optimum performance or special feature.

“Analog Mixed Foundry – Today & Tomorrow” — Michael Lehnert, CEO, Landshut Silicon Foundry

The semiconductor foundry market is expected to rise to $40B per annum by 2013 growing at about 25 percent today, but slowing to five percent by the end of the forecast. The bulk of the growth is by ‘pure-play’ foundries and in process geometries finer than 90nm, although the coarser geometry revenue does not shrink.

The first ever Future Horizons Business To Business Speed Networking opened this year’s forum. This fast paced networking session really set the scene for the rest of the forum, helping delegates to establish relationships from theoutset, as well as putting delegates in high spirits.

Opportunities for LFoundry are in 350nm, 250nm, 180nm, and 130nm geometries, where prices are stable and unit volumes are up. Europe depends heavily on the automotive and wireless markets and these are driven by increased customer requirements and system integration in these technologies. It is in system integration and multi-chip designs where there is a high demand for analog solutions.

Analog foundries differ from their digital counterparts in that the specifications have more parameters to meet and this means that the process has to be more characterised. Analogue foundries often have coarser geometries and 6-inch or 8-inch wafers rather than the digital 12-inch and these specialised foundries are moreflexible to customer requests, although this means they are more expensive.

“Designing For The Upturn: Exploiting Industry Dynamics To Ensure Success” — Hossein Yassaie, CEO, Imagination Technologies

Imagination Technologies is a supplier of semiconductor IP into the graphics, mobile phone and internet markets. Hossein points out that in this age ‘you either win big or lose big’ in these huge Internet and mobile connectivity markets.

Companies have to keep on top of changing business models and changing supply chains to have a successful business. Every two to three years you have to have new products, new philosophies, new markets and new customers. Technology evolves and what could be done on four chips, MPEG decoding, say, can now be done on one, and the new single chip has improved also to have high definition!

Consumers are involving. They want everything effortless. They want to have entertainment and communications everywhere at anytime. The ‘Apple effect’ has raised every consumer’s expectations – users want easier to use product interfaces.

The mobile phone world order is changing. Instead of Nokia, Ericsson and Motorola people are saying iPhone, Blackberry and Android. These are the new platforms for which suppliers are developing software and hardware, replacing the original PC universal platform development activity. Video is everywhere and YouTube has generated user-supplied content. TV broadcasters, such as the BBC, are now generating content available everywhere/anytime.

Designing IC products for the upturn must include connectivity, multimedia and these in lower-power SoC form. Connectivity is not an option but a must have it integrated into the chip. The same about low-power so with an SoC IC design a small power consumption must be part of the specification from day one.

For the SoC designer many functions are available in IP form so for small start-up companies the important issue is ‘domain knowledge’. This specialist expertise plus available mature and proven IP is the way ahead for the next generation of companies as long as they do not shy away from partnerships and be open and realistic about their abilities.

“Don’t Fear The Exponential”, Joe Sawicki, Vice President D2S Division, Mentor Graphics

Over and over again industry commentators has said that chip makers cannot afford the cost of the next generation of IC design or the fabs needed to build them. In 2007, ITRS forecast that SoC chips would cost $40M in 2009 and $100M in 2012, but this did and will not happen. In 1798, Malthus forecast the world’s population growth completely wrong. In 1968 Paul Ehrlich said that we would all starve by 1990, but food resources coped. Why we get these predictions wrong is because of human innovation triggered by fear that something needs to change.

For the same reason Joe explained that mask design costs for 32nm are already less expensive than 45nm in 2007. Innovations in system design will offset the predictions in this area. Innovations in EDA software will allow improvements in chip architectural design and computer exploration of hardware/software options will lead to shorter timescales. More use of higher-level synthesis will reduce verification and debugging, and virtual prototyping and graphics automation tools will reduce engineering costs.

 

The semiconductor world was horrified looking forward at design costs, but should now see it as an opportunity to make organisational changes, and work to embrace rather than fear the exponential.

(To be concluded!)

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