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Cadence Virtuoso IC6.1.4 design platform comes with several enhancements

December 14, 2009

Last week, Cadence Design Systems Inc. introduced the Virtuoso IC6.1.4 — with dramatic improvements to the Virtuoso IC design platform — that reduces overall design time and ensures high-quality production ICs.

These enhancements are said to benefit design teams working along the full spectrum of design complexity, from the most advanced-node, cutting-edge designs to more traditional chips.

This release has been extended to work efficiently at advanced nodes down to 28 nanometers and now supports 64-bit processing for improved capacity and performance. The Virtuoso Space-Based Router has been integrated into the Virtuoso Layout Suite cockpit, making it easier to access.

I got into a conversation with Steven Lewis, marketing director, Cadence, to find out more about this release.

Steven Lewis, marketing director, Cadence Design Systems.

Lewis said: “Virtuoso IC61 was first shipped in October, 2006, over three years ago. IC614 is the latest release of this platform. IC61 is based on OpenAccess as a database with a Qt based GUI. Also, in IC61 a common design constraint system is key to design spanning schematics, layout, routing, circuit optimization, and all other Virtuoso applications.”

The IC 614 has a number of significant areas of enhancements. These include:

1) Significant improvements to analog design environment
— A number of key enhancements have gone into ADE to make it even easier to use and to improve performance. Areas like: data presentation, multi-testbench support, analysis and signoff quality validation, data sheet generation, simulation results comparisons, and intelligent selection of sensitivity to statistical variations to dramatically reduce the number of simulations needed.

2) Native integration of the Catena interconnect engine
— This enables integration of the Cadence Space-based Router into VLS-GXL, including the common design-constraint system, runtime OA database and OA techfile for design rules. In addition, the Wire Editor, which is based on this technology, is available to every VLS XL Layout Designer.

3) Metric-Driven Productivity
— IC 6.1.4 is all about productivity, productivity, productivity. Many users of VLS spend six to eight hours a day in front of this cockpit and incremental improvements have a significant cumulative effect. IC 6.1.4 will:
* Reduce the mouse miles that a layout designer sees.
* Reduce the mouse clicks required for an operation.
* Reduce the menu depth for an operation.

And, how will the IC6.1.4 gain capacity, performance and usability boosts to shrink design cycles?

According to Lewis, there are a number of enhancements to frequently used features, like a new Layer Palette, improved Repeat Copy, enhancements to Via Placement, a new Smart Ruler, and PCell Caching. Additionally, there are improvements to the connectivity, constraint-aware editing and verification, and capacity with the 64-bit port.

Addressing other new design constraints
How much is this tool specifically geared to address sub-45-nanometer design yield challenges and so on?

Lewis said that Cadence had teamed up with other leading companies on 32nm design-rule constraints, and how these are represented in the OA tech file. This work will drive things like the Space-Based Router and design-rule-driven editing. Cadence has proposed to the Si2 the donation of this work with the approval of the collaborating companies.

The benefit of advanced node design rule support in the OA tech file is the interoperability with any OA-compliant tool that needs these rules defined to run. The router is a simple example. Any OA-based router will be able to access these design-rule constraints. This eases set-up for customers.

Design constraints easier to enter, manage and verify — Designers now have a robust assistant to aide the application of constraints. This makes the process of adding constraints like matching much faster. The ability to back-annotate layout constraints to the schematic has been improved. And finally, the ability to programmatically verify constraints is available. This will eliminate the manual checks that are done now, regardless of whether the design was manually laid out, or used some automation.

New 32nm rules donated to Si2 OpenAccess — This will provide all consumers of the 32nm design-rule constraints who use the OA tech file to leverage the work that Cadence accomplished and enable advanced editing and automation.

Cadence’s new PDK development intiative
I requested Steven Lewis to elaborate briefly on the new PDK development initiative inside Cadence in 2010, especially in terms of what it will achieve.

He said: “Today, there are over 100 SKILL-based foundry PDKs available for IC6.1 including advanced node and mature nodes from 28nm à 1.2um from TSMC, IBM, Jazz/Tower, UMC, Chartered, XFab, and others.

“In 2010, we will focus on direct engagement with resources for foundries, IDMs, and fabless companies to ensure that complete available for IC 61, SKILL-based PDKs. In addition, Cadence is also focused on providing PDK developers with a solution consisting of new functionality and existing applications for the development of object-oriented SKILL PCells and IC 61 PDKs.”

Finally, why release such solutions in patches?? Couldn’t these be handled in earlier releases? Lewis noted: “Releasing new technology in patch upgrades is common in the software industry. It is a way to get important new technology to customers as quickly as possible.”

Does this solution solve all of the serious EDA challenges? While Lewis agreed that no single EDA solution will solve all of the serious EDA challenges, he added, “We believe this release represents a significant step forward in custom IC and mixed-signal design, but there remains plenty of work to keep EDA engineers busy in 2010.”

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