TSMC enables business growth through effective and collaborative innovation
While speaking on ‘Enabling business growth through effective and collaborative innovation’, at the recently held International Electronics Forum (IEF) 2010 in Dresden, Germany, Dr. Jack Sun, CTO and vice president, R&D, TSMC said that TSMC leads and invests heavily in competitive, energy efficient, and eco-friendly technologies to enable product innovation, such as CMOS platform scaling (40/28/20nm/FinFET, low-R,ELK..), More-than-Moore, and integrated package/3D-IC.
He added that TSMC strives for manufacturing excellence and capacity, and economy of scale, to support customers’ innovation and business growth. The company is also pushing the acceleration of EUV and Multi-Ebeam capabilities for cost-effective density scaling. His clear message was, “We must and can collaborate to innovate and overcome the technical and cost challenges.” That is, a collaborative innovation among the government, the industry and the academia is required to overcome the cost hurdle.
Earlier, he said that the IC industry will continue to grow — with a 22 percent growth likely in 2010, reaching $276 billion. During 2011-2014, he estimated a 4.2 percent CAGR for the IC industry and 7.2 percent CAGR for fabless companies.
Dwelling on the application and technology trend, Dr. Sun pointed out that the trend is SoC and heterogeneous integration at chip, package, and product level with embedded power-efficient processors, hardware accelerators, and special features.
TSMC continues to further expand its offering by including packaging services and silicon foundry services. This will allow the fabless semiconductor companies to achieve ‘More than Moore’ gains in integration by using TSMC as a foundry partner.
Dr. Sun also detailed the how TSMC enables innovation by providing best-in-class technology and design solutions.
TSMC’s 20nm and 28nm leadership
While on TSMC 28nm technology highlights, Dr. Sun said that the 28LP (poly/SiON) yield is approaching mature level on 64Mb SRAM. Also, the 28nm HKMG (28HP/28HPL) development is on track. Here, TSMC developed Gate-Last process with N+/P+ work function and superior performance, yield, manufacturability, variability,and reliability.
Also, it achieved double-digit 64Mb yield, good Vccmin, close-to- targets transistors, and good pre-qual reliability.
Now, on to TSMC’s 20nm highlights. The key technology features include planar transistors with 2nd-generation HKMG and 5th-generation strained Si; low-resistance ultra-shallow junction with M0 and enhanced millisecond anneal and silicide; and enhanced ELK and 2nd-generation Low-R interconnect.
Some other 20nm tehchnology highlights include immersion lithography with innovative patterning and layout solutions to achieve 2x density over 28nm, with the EDA tool likely to be ready by mid 2010. Also, the design rules are compatible for EUV and Multi-Ebeam insertion for selected layers in 2013-2014. Wow, this is really something!
Dr. Sun also touched upon the Multi-Ebeam maskless lithography at TSMC. The MAPPER pre-alpha tool (110 beam, 5KeV) has been at TSMC since July 2009. It has accomplished 10 percent beam-to-beam CD uniformity for 45-nm half-pitch and 30-nm half-pitch for contact holes. This will be upgraded to 13,000 beams for 10 WPH, and clustered for 100 WPH for N20 and N14.
He listed TSMC’s manufacturing leadership as follows:
On the N40 volume production ramp, Dr. Sun said that two giga-fabs are in volume production with good D0 and device performance.
Also. two of TSMC’s parallel capacity building lines will stay as 12” capacity leader — referring to Giga Fab 12 and Giga Fab 14, respectively. TSMC is determined to continue expanding capacity. Fab12 Phase 5 — planned tool move-in in 3Q‘10; Fab12 Phase 6 — secured land; and Fab14 Phase 4 — ground breaking in 1Q10.
Dr. Sun talked about how TSMC aims to achieve cost effective manufacturing through 450mm production as well.