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Xilinx announces first stacked silicon interconnect technology

October 28, 2010

Xilinx Inc. announced the industry’s first stacked silicon interconnect technology. It proposes to deliver breakthrough capacity, bandwidth and power savings using multiple FPGA die in a single package for applications that require high-transistor and logic density, as well as tremendous levels of computational and bandwidth performance.

3D packaging approach

L-R: Xilinx's Dave Myron, Suresh Ramalingam and Neeraj Varma discuss the first stacked silicon interconnect technology.

L-R: Xilinx's Dave Myron, Suresh Ramalingam and Neeraj Varma discuss the first stacked silicon interconnect technology.

Xilinx has taken a 3D packaging approach that makes use of passive silicon-based interposers, microbumps and through-silicon vias (TSV) to deliver multi-die programmable platforms. As the interposer is passive, it does not dissipate any heat beyond what’s consumed by an FPGA die.

The stacked silicon interconnect technology offers 2X FPGA capacity advantage at each process node. It is a core part of Virtex-7 family. Also, the stacked silicon interconnect technology is supported by standard design flows.

Xilinx has been accelerating FPGA transition to the heart of the system. David L. Myron, senior manager, High Volume Products, Product and Solutions Management, Xilinx, revealed that a lot of Xilinx’s customers are doing FPGA starts rather than ASIC starts as that seems more viable. Customers are now asking for much more — over 2X today’s logic capacity, many more high-speed serial transceivers as well as processing elements, as well as much more internal memory to store data. “The challenge is delivering ‘more than Moore’,” he said.

Myron cited certain challenges. These include availability and capability — the largest FPGAs are only viable later in the life cycle. Power and bandwidth pose additional challeges. The traditional mitigation techniques are no longer adequate. “One of the trends we have seen is that while gate count has gone up at a certain rate, the I/Os have not,” he added. Hence, innovation is the need of the hour to meet capacity requirements.

The stacked silicon interconnect technology is addressing all of these challenges, meeting the needs of high bandwidth, low latency and low power. This Xilinx innovation offers massive number of low latency, die-to-die connections. Besides, there is no wasted I/O power.

For applications requiring high-transistor and logic density for high levels of computational and bandwidth performance, these 28nm platforms will deliver significantly higher capacities, resources and power savings than possible in a monolithic die approach.

FPGA architectural innovation key
Suresh Ramalingam, director, Package Design and Advanced Package Development, Xilinx, said that Xilinx’s FPGA architectural innovation has been at the heart of the technology. FPGA slices — which are ASMBL (application specific modular blocks) optimized FPGA slices — are placed side by side. Use of silicon interposer enables high bandwidth connectivity. He added, “We have enabled direct connections to the logic region.”

Xilinx stacked silicon interconnect diagram.

Xilinx stacked silicon interconnect diagram.

The stacked silicon interconnect technology harnesses proven technology quite uniquely — such as microbumps, TSV, passive silicon interposer (65nm) and side-by-side die layout. The technology enables 100x bandwidth/watt advantage over conventional methods. It also delivers feature-rich FPGAs.

Ramalingam added: “Going from  40nm to 28nm, there is 3.5X times improvement in logic cells. When we bring 28nm to market, we will have another 2.8X advance in capacity. Xilinx is providing optimized ISE design suite flows for a variety of users.

With software support available from Xilinx in ISE Design Suite 13.1, currently available to beta customers, the 28nm Virtex-7 LX2000T device will be the world’s first multi-die FPGA and provide over 3.5X logic capacity of the largest current-generation Xilinx 40nm FPGA with serial transceivers and 2.8X the logic capacity of the largest competing 28nm FPGA with serial transceivers. Initial devices will be available in the second half of 2011.

Xilinx has benefitted by collaborating with technology leaders such as leading fabless and fablite companies, equipment manufacturers, fabs and OSAT, as well as industry consortia such as imec, Sematech, SEMI, etc.

The India launch was held today, October 28th, while the Taiwan launch was two days ago.

Neeraj Varma, country manager, Sales, for India and Australia and New Zealand, Xilinx, was kind enough to share details of the ISE Design Suite 12.3, which I will post later.

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  1. Dr. Tim Majumdar
    October 29, 2010 at 6:15 am

    (via LinkedIn)

    Stacked silicon is one of five or six major ways to get the spatial density of a 3D IC. Am afraid most of the stacked 3D interconnect patents are already filed by IBM years back. It will be hard for anyone to make a deep foray into it without running foul of IBM.

  1. October 29, 2010 at 12:16 am
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