STMicroelectronics unveils STM32 F-2 series of MCUs

December 1, 2010

STM32 F-2 block diagram.

STM32 F-2 block diagram.

STMicroelectronics has unveiled its roadmap for ARM Cortex-M4 and -M0 with products sampling from mid 2011 onward and production by end of 2011. It has also unleashed the full performance of the Cortex-M3 with its latest STM32 F-2 series.

According to Vinay Thapliyal, technical marketing manager, MCU, STMicroelectronics, India, there are over 30 new part numbers, pin-to-pin and software compatible with existing STM32 devices.

He said: “Today, we already have 110 parts running for the F-1 series, which is currently existing and in full production. Now, we are extending the family. This time, we have launched the F-2 family — the highest performance family — to unleash the ultimate performance of Cortex-M3.” Naturally, the F-2 series is benefiting the existing F-1 devices.

As mentioned, 30 new devices will be launched. They are already ramping now. “All of these belong to the high-performance, low-power family. We will also be revealing our roadmap for M4 and M0 — to be  in production by end of 2011, with sampling by middle of 2011.”

ST’s F-2 series will further enhance real time preformance. Thapliyal added that ST has built in ART accelerator into these devices. This will deliver 150 DMIPS (Dhrystone MIPS) at 120MHz.

The adaptive real-time memory accelerator unleashes the Cortex-M3 core’s maximum processing performance equivalent to 0-wait state execution Flash up to 120 MHz.

The ART accelerator is a pre-fetch queue and branch cache mechanism that stores the first instructions and constants of the branches, interrupt and subroutine calls. The penalty occurs the first time those events occur like for any pipelining mechanism.

After that, the instructions stored in cache are pushed immediately in the pref-etch queue upon recognition of a stored branch address. In addition, the embedded Flash is organized in 128-bit rows, allowing up to 8 (16-bit) instructions to be read per access.

Key benefits of the STM F-2 series includes future proof design, environment friendly and suitable for low power operation, makes use of superior and innovative peripherals, maximum integration, and availability of extensive tools and software.

New features include:
* 20 MHz running CPU with  ART Accelerator and  multi-level AHB bus matrix.
* 1.65 to 3.6V supply.
* 1-MByte Flash, 128-KByte SRAM.
* 4 Kbytes back up SRAM.
* Ethernet, 2xUSB OTG with high speed support, camera interface.
* Crypto/Hash processor.
* True random number generator.
* Fast ADC 2MSPS.
* 32-bit timers.

Thapliyal added: “With the F-2 series, we have further improved on the peripherals. We have added high-speed USB OTG, camera interface, Ethernet, crypto/hash processor and external memory interface, etc. We also have 3 SPIs running at up to 30 Mbit/s.

“We have also built in maximum integration — 1Mb of Flash, 128Kb of SRAM, and 528 bytes of OTP, 4Kb of backup SRAM, etc. Hence, a lot of memory enhancement has been done for maximum integration.”

The peripherals include:
* High speed USB OTG.
* Audio architecture: I²S and USB peripherals with advanced dual PLL and data synchronization schemes.
* Camera interface, 8- to 14-bit parallel, up to 48 Mbyte/s at 48 MHz.
* Flexible static memory interface running at up to 60 MHz to expand memory space or support an external display.
* Crypto/hash processor: 3DES, AES256/SHA-1, MD5, HMAC.
* 3 SPIs running at up to 30 Mbit/s.* 6 USARTs running at up to 7.5Mbit/s.
* 3x 12-bit ADC, 2 MSPS, up to 6MSPS in interleaved mode.True random-number generator.Fast GPIO (60 MHz toggling speed).

The addition of 30 new devices — leading to 180 pin- and software-compatible devices, will complete the portfolio.

As per Thapliyal, the addition of fast ADC 2MSPS will be helpful for development — analog signals can be processed  very fast — in less than a nanosecond. “We have devices starting from 64-pin up to 176-pins, and memory from 128Kb to 1Mb.”

Real-time performance also gets enhanced — 32 bit multi-AHB bus matrix — by integrating the different peripherals together. As for power efficiency, it will give 188 µA/MHz, 22.5 mA at 120 MHz executing from Flash memory. This device family is on the 90nm process, which allows running at 1,2V.

Contribution of power efficiency has been done with advanced low power modes, which makes less than 1mA with RTC on.

Applications served by the STM32 F-2 series include point of sale/inventory management, industrial automation, security applications, building automation, medical, T&M eqiuipment, transportation, etc. According to Thapliyal, the evaluation kit is now available for development.

STM32 roadmap
As for the STM32 roadmap, he added that post the F2 launch, ST will be coming out in 2011 with the Cortex M0 family targeting 8- and 16-bit applications, as well as the  Cortex M4 – targeting 32-bit applications, along with DSP applications.

Some devices from the M0 and M4 family should be available by the middle of 2011. These will be in production by the end of the year.

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