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EDA and emerging system design challenges: Dr. Wally Rhines

December 10, 2010

Dr. Wally Rhines.

Dr. Wally Rhines.

According to Dr. Walden C. Rhines, CEO and chairman, Mentor Graphics, the emerging system design challenges likely to shape the industry in the coming decade are:

* Design for low power.
* Optimizing for performance and power.
* Functional verification complexity explosion.
* Place and route timing and power closure.
* Physical verification complexity.
* Manufacturing yields.
* Increasing cost of design.
* Macro system integration.

He was delivering the keynote titled EDA and emerging system design challenges at Mentor Graphics’ U2U India conference in Bangalore.

First, Dr. Rhines highlighted that the EDA market churn is often confused with industry consolidation. EDA requires specialization. The #1 supplier in each EDA product segment averages 66 percent+ market share. However, the traditional EDA market has not been growing.

EDA market snapshot
The synthesis market trend has seen a 2.7 percent CAGR, with a 10-year average of $293 million. The market size was $273 million in 2008, and slid to $243 million in 2009. In 2010, after the first two quarters, it is approximately $125-$130 million.

The RTL simulation market trend has seen a -0.3 percent CAGR, with a 10-year average of $365 million. The market size was $394 million in 2008, and slid to $345 million in 2009. In 2010, after the first two quarters, it is approximately $150 million.

The IC layout verification market trend has seen a 0 percent CAGR, with a 10-year average of $199 million. The market size was $199 million in 2008, and slid to $187 million in 2009. In 2010, after the first two quarters, it is approximately $80-$90 million.

The IC physical implementation market trend has seen a 2.4 percent CAGR, with a 10-year average of $559 million. The market size was $549 million in 2008, and slid to $448 million in 2009. In 2010, after the first two quarters, it is approximately $210 million.

The total PCB/MCM design market trend has had a 10-year average of $484 million. The market size was $535 million in 2008, and slid to $490 million in 2009. In 2010, after the first two quarters, it is approximately $220 million. PCB design has seen growth from analysis, design for manufacturing and new emerging markets.

Dr. Rhines indicated that the global designer population growth is increasing. Asia is the only growing region in EDA. During 2000-2009, growth has been 11 percent in Pac Rim, 2 percent in Europe, 1 percent in Japan and -1 percent in America.

EDA TAM growth. Source: Mentor Graphics

EDA TAM growth. Source: Mentor Graphics

EDA TAM growth is driven primarily by emergence of new markets. Most EDA revenue growth comes from major new design methodologies. The areas that grew during 2000-2009 are DFM- 33 percent CAGR, ESL — 12 percent, Formal verification – 11 percent, IC/ASIC analysis – 9 percent, respectively. System level issues have also become a bigger part of chip and board design.

“System” level issues are now becoming a bigger part of chip and board design.

Emerging system design challenges shaping the industry
As mentioned, Dr. Rhines outlined eight critical and emerging system design challenges.

Design for low power
Low power acts as the differentiator. For example, the difference between iPhone 3 and iPhone 4 is the latter’s battery life. There is a need to attack low power at all levels. There is the Unified Power Format (UPF) compatible verification. Its verification methodology identifies all power domains/modes. It adds assertions to verify proper data retention and reset behavior. Also, UPF ensures high coverage on all power-related assertions.

What has not become routine is the embedded system-level power management. There are things such as power aware drivers, reactive power management and even proactive power management — predict what the power use needs are before you need them.

Next, the choice of RTOS can make a significant impact on the power budget. Hardware/software tradeoffs also impact power and performance. There are micro-architecture power tradeoffs as well. There is the IEEE 802.11a standard for wireless.

Power issues also extend to the board. ICs create power challenges at the board level. PCB power distribution networks are even more complex. A comprehensive thermal simulation is required – IC package, PCB, system.

Optimizing for performance and power
System level optimization has biggest impact on performance and power. ESL provides the next design abstraction. It provides fast hardware/software validation platform, as well as more opportunity for architectural exploration. The architectures are optimized before committing to RTL.

Functional verification complexity explosion
Verification has been falling further behind. There is a need for exponential growth in capabilities to keep pace, as there has been a 10X increase in number of transistors that requires 1000X increase in verification. The solution –comprehensive digital verification flow.

There are three approaches to test benches — directed tests, constrained random tests and intelligent tests. Another area causing revolutionary change is hardware-assisted verification. It acceslerates system verification and enables dual mode operation. It also delivers simulation like look-and-feel.

Place and route timing and power closure
Concurrent power and timing closure is required for complex designs. The solution lies in MCMM (multi-corner, multimode). Complexity grows as more domains are added. One pass with MCMM can handle 100s of operational modes and corners.

Speed gains are possible through multi-threadding. Another thing happening is integrating place and route with physical verification.

Physical verification complexity
The solution to this problem lies in accelerating the manufacturing closure. Physical verification is changing. Calibre PERC: is verifying circuit reliability and identifying areas of electrical failure. Calibre xACT 3D provides reference-Level accuracy and design-scale performance.

As for implementation technology — 3D packaging options are available. The three most common approaches are — stacked die, PoP )package on package) and 3D IC with TSV interconnect. The Calibre TSV verification is available today.

Manufacturing yields
The solution lies in yield-centric design and verification flow. There is a pervasive design for manufacturability.

Increasing cost of design
The SoC design costs are forecasted to exceed $100 million within three years. The solution for this challenge lies in embedded software automation (ESA).

Macro system integration
The solution lies in distributed system design with model driven design. Electronics becomes half the total cost and more than half the design issues. 

Why India for R&D despite increasing costs?
Dr. Rhines also touched upon Mentor’s continuing interest in India. He listed several reasons:

* India’s technical educational system is among the most competitive in the world. This continues to grow. That base is sought after.
* India boasts the second highest number of university graduates per year. Also, 70 percent of the recent IIT graduates now stay in India.
* India’s executive talent is world class.
* India’s research publications are growing at a rapid pace. There has been an increasing research output from India.
* Indian electronics engineers are younger and they are likely more open to new methodologies.
* IIndia electronics production is also growing at double digit rates.
* India venture capital investment has also been growing.* India is ranked as the world’s top destination for outsourcing activities.
* In the 2010 FDI confidence index, India is ranked third behind China and USA.

Dr. Rhines concluded: “We feel that we are in a good place, We enjoy the innovation here.”

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  1. Dr. MP Divakar
    December 10, 2010 at 6:04 pm

    Pradeep, thanks for the write up. The message from Dr. Rhines was almost identical at the U2U earlier this year in the Silicon Valley. Mentor actively participates in GSA’s 3D standardization efforts (I am a part of it as well) so I am surprised that 3D designs are not in the list of design challenges (though it is mentioned some what later in your writeup):

    * Design for low power.
    * Optimizing for performance and power.
    * Functional verification complexity explosion.
    * Place and route timing and power closure.
    * Physical verification complexity.
    * Manufacturing yields.
    * Increasing cost of design.
    * Macro system integration.

    Perhaps, 3D design challenges can addressed under all of the above! However, the tools are lacking as I have been hearing from many end users. Partitioning, placing and routing in 3D (addressing power, timing/clock tree, thermal/mechanical, reliability-aware) is no easy feat and tools are badly needed.

    Dr. MP Divakar

    • December 11, 2010 at 2:09 pm

      Quite right sir! 🙂 And yes, 3D design did come up later. I’ve only given the salient points here. Regards.

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