Home > EDA, global semiconductor industry, global semiconductor market, Mentor Graphics, Semiconductors, Walden C. Rhines > Mentor’s Wally Rhines on global EDA industry challenges – I

Mentor’s Wally Rhines on global EDA industry challenges – I

December 14, 2010

Dr.  Wally Rhines, CEO and chairman, Mentor Graphics.

Dr. Wally Rhines, CEO and chairman, Mentor Graphics.

It has always been such a pleasure meeting Dr.  Walden (Wally) C. Rhines, CEO and chairman, Mentor Graphics Corp. During his recent visit to India, I managed to enter into a discussion with him regarding various issues facing the global EDA industry.

Part one of the discussion looks at the industry, as well as EDA related issues such as predictability, verification and IP integration, how can Mentor help start-ups address EDA challenges, and going about software-to-silicon verification. May I also take this opportunity to thank my good friend, Mentor’s Veeresh Shetty.

I began by asking Dr. Wally Rhines about the fortunes of the global EDA industry and what’s it going to be like in 2011?

He said: “The EDA industry typically follows the recovery in semiconductor industry R&D spending by six to 12 months. Mentor’s strong results in Q3 (with 60 percent growth in bookings) suggest that the recovery has already started. In our third quarter conference call, we indicated to our investors that 2011 looks like a good year as well.” 

Improving predictability of design process
Coming to the EDA industry challenges, how much has EDA helped improve the predictability of the design process? Dr. Rhines said: “Well, since few, if any, do design without EDA, quite a lot! More seriously, there have been a great number of advances in the last few years that have really improved predictability.

“From intelligent test benches and emulation,that dramatically improve the verification of design, to advanced design-for-manufacturing and yield analysis techniques that greatly improve predictability of results and manufacturability in the back end.”

Verification focus and need for ESA
Have the EDA tools made verification process cost effective and focus on design as well as IP integration? According to him, the cost of design really hasn’t changed that much in the last decade, at least in terms of hardware design. “So, I think that says that we have been pretty effective as an industry in delivering cost effective design tools. In fact, the EDA software cost per transistor has decreased as fast, or faster, than the other “input” cost of semiconductors like manufacturing equipment, materials, etc.

“Evolution of third-party IP also has decreased the cost of creating SoCs and the EDA tools to integrate and verify that IP have kept pace with the increase in IP block complexity. The increase in chip development cost that designers have experienced is largely the result of the growing cost and complexity of embedded software. We need more ESA (Embedded Software Automation) to complement the benefits of EDA.”

Helping start-ups face EDA challenges
I have been aware of a few small firms and other startups using EDA tools who would like to find a way to make their EDA suppliers become more aware of the issues and challenges they face. So, what’s Mentor doing about this?

Dr. Rhines said: “Well, we are quite proud of Mentor Support. It has won many awards, and through it we regularly hear from our customers on their issues. Of course, we also work closely with our customers on their design challenges.

“EDA companies like Mentor are always looking for new challenges; if a design group has a challenging design, we are always glad to hear about the issues that they are encountering.  In addition, we are always looking for good “beta” customers for innovative new EDA software. So, I recommend that the designers let their EDA account manager(s) know if they are interested in participating.”

Software-to-silicon verification
How is EDA going about addressing software-to-silicon verification? Dr. Rhines elaborated that companies like Mentor are providing complete verification ‘platforms’. Intelligent test benches are offering one to three orders of magnitude improvement in coverage or speed.

He said: “Formal methods, like clock domain crossing, are solving verification problems that couldn’t be verified with the traditional approaches. OVM provides a methodology that is rapidly becoming a standard for how to put together a verification methodology.

“Embedded assertions are providing improved coverage and coverage metrics have become standardized. Most importantly, hardware acceleration is rapidly becoming a required tool for large designs and its adoption is becoming widespread. I would not be surprised to see the hardware acceleration market double in size this year. ”

Part II of this discussion follows tomorrow.

Advertisements
%d bloggers like this: