Archive for October 2, 2011

Semiconductor supply chain dynamics: Future Horizons @ IEF2011

The last decade heralded a dramatic transformation in supply chain dynamics, driven by the complexity challenge of staying on the More Moore curve. On the demand side, the high cost of fabs persuaded almost all integrated device manufacturers (IDMs) to use foundries for their leading-edge wafer supply.

The ever-increasing process complexity and its negative impact on manufacturing yields forced the adoption of sophisticated foundry-specific design-for manufacturing (DFM) techniques, effectively committing new chip designs to a single foundry and process.

At the same time, the industry adopted a much more cautious lagging rather than leading demand approach to new capacity expansion, resulting in under-supply and shortages in leading-edge wafer fab capacity. To make matters worse, the traditional oxide-based planar transistor started to misbehave at the 130nm node, as manifested by low yields and higher than anticipated power dissipation, especially when the transistors were supposed to be off, with no increase in performance, heralding the introduction of new process techniques (e.g., high-k metal gates).

Even before these structural changes have been fully digested, supply chain dynamics have been further disrupted by the prospective transition to 450mm wafer processing, to extreme ultra violet (EUV) lithography, and from planar to vertical transistor design.

Transistor design
Since the start of the industry, adding more IC functionality while simultaneously decreasing power consumption and increasing switching speed—a technique fundamentally known as Moore’s Law—has been achieved by simply making the transistor structure smaller. This worked virtually faultlessly down to the 130nm node when quite unexpectedly things did not work as planned. Power went up, speed did not improve and process yields collapsed. Simple scaling no longer worked, and new IC design techniques were needed.

While every attempt was made to prolong the life of the classic planar transistor structure, out went the polysilicon/silicon dioxide gate; although this transition was far from plain sailing, in came high-k metal gates spanning 65nm-28nm nodes. Just as the high-k metal gate structure gained industry-wide consensus at 28nm, it too ran out of steam at the 22nm-16nm nodes, forcing the introduction of more complex vertical versus planar transistor design and making the IC design even more process-dependent (i.e., foundry-dependent). Dual foundry sourcing, already impractical for the majority of semiconductor firms, will only get worse as line widths continue to shrink. Read more…

Welcome to Durga Puja @ Jayamahal, Bangalore!

Ya Devi Sarva Bhutey Shu…
Shakti Roopena Sanasthitha
Namas tasyai,  Namas tasyai, Namas tasyai, Namo Namaha!
To the goddess who abides in all beings as power: Salutations to thee!

Durga Puja @ Jayamahal, Bangalore.

Durga Puja @ Jayamahal, Bangalore.

Friends, welcome to Durga Puja @ Jayamahal Extension, Bangalore! Today is Maha Shashti, the first day of the Puja. Goddess Durga is awakened from slumber in a program known as ‘Agomoni’. She then goes on to slay the infamous ‘Mahishasur or the demon king’!

In Hindu mythology, it is said that the evil Mahishasur started terrorising Heaven and earth. He invaded heaven, defeating Indra, the king of Gods, and drove all the other Gods out of heaven. This led the Gods to convene a meeting and come up with Goddess Durga. She fought with the Mahishasur for nine days. On the 10th day, Goddess Durga finally killed Mahishasur, who had taken refuge in the shape of  a Mahish (buffalo).

Given here is a map – with driving directions – to Jayamahal Durga Puja, Bangalore.

Naturally, I am involved here. Should you happen to drop by on any of the next three days, especially during afternoon Bhog, or community lunch, I may even serve you! 😉

Welcome, my dear friends, to the 2011 Durga Puja celebrations @ Jayamahal Extension, Bangalore.

Categories: Bangalore, Durga Puja
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