Lattice intros low power ECP4 FPGAs
Lattice Semiconductor Corp. has introduced the low-cost and low-power ECP4 FPGAs. These feature 6Gbps SERDES in low cost wire-bond packages, powerful DSP blocks and hard IP-based communication engines for cost- and power-sensitive wireless, wireline, video, and computing markets.
The LatticeECP4 FPGA family features high performance, low power in low cost 65nm process, making a great FPGA family even better. Lower cost, high yield 65nm process is ideal for mid-range FPGAs. There has been an extensive use of wire-bond packaging. The FPGAs have CDR capable I/Os that lower customers’ implementation cost. The POWER sysDSP minimizes multipliers and LUTs, and enables high bandwidth in a small area. There is also a 10X area reduction by use of hardened MACO communication engines.
The ECP4 features lower power architecture. It is optimized for mid-density devices, and not based on high-density high overhead platform. Modified logic/routing power ratio helps achieve higher performance with modest dynamic power increase. It also features higher bandwidth and performance.
As it is, the FPGA boasts 10X more efficient hard MACO engines. Besides, it has 7X more DSP processing capability, 2X faster SERDES (6G), 66 percent more LUTs, 50 percent higher LVDS performance, 42 percent more memory and 33 percent higher DDR3 I/O performance.
Diamond 1.4 beta design software is available for select customers, especially those who jumpstart cost-effective platform designs. The ECP4 device samples will be available in 1H 2012, and the ECP4 production devices will be available in 2H 2012.
Features include high performance for low cost — such as up to 250K LUTs, multi-protocol CEI compliant 6G SERDES, 30 percent faster fabric, 42 percent more embedded memory, 50 percent faster GIGA sysIO with CDR capability, MACO communication engine hard IP and innovative power sysDSP with 4X bandwidth.
For low cost and low power, the FPGA uses mature, low cost 65nm process. There is an extensive use of wire-bond packages as well as of hard IP. It is architected specifically for mid-density devices and beats power dissipation of more “advanced nodes”. Finally, there is low cost of ownership. The MACO engines save 10X power and footprint. The GIGA sysIO is CDR capable I/O and saves SERDES. The power sysDSP is breakthrough signal processing using less LUTs and multipliers. Innovative low cost wire-bond packaging supports 6G SERDES, 1.25Gbps LVDS w/ CDR and 1066Mbps DDR3.
End market and equipment
The end market and equipment includes wireless access — multimode remote radio heads (RRHs) and multimode base stations. Here, the key requirements are powerful signal processing to linearize MIMO based RRH, high performance SERDES for RRH and baseband connectivity, and optimized CPRI low latency variation support. The key ECP4 features include power sysDSP that provides 7X improvement, MACO communication engines — SRIO2.1 x4, PCIe2.1 x4, 12 EMACs, 2 x EMAC10G, and specialized CPRI interface.
Another area is wireline access, such as wireless backhaul, wireline access, switches and routers, and storage and computing. Here, the key requirements include high bandwidth Ethernet support for data plane, multiple high speed DDR3 interfaces, and PCIe 2.1 for next gen control plane. The key ECP4 features include Ethernet MACO engines that support 10G, 2.5G and 1G, 1066Mbps DDR3 and SGMII on GIGA sysIO, and PCIe 2.1 x4 MACO engine.
A third area is video edge, such as professional video equipment, industrial and surveillance cameras, and digital signage. Here, the key requirements are high bandwidth signal processing, multi-data rate SERDES and multiple high speed DDR3 interfaces. The key ECP4 features include Cascading and Symmetry to support large FIR filters, SERDES supports 155Mbps without oversampling and 1066Mbps DDR3 support, respectively.
Lattice’s Diamond design software has been built for cost sensitive, low power applications. Features include ease of use throughout, new system planner tool that optimizes resource usage and power calculator with static and dynamic low power modes.