Cadence Design Systems recently introduced the latest release of Cadence Encounter RTL-to-GDSII flow for high-performance and giga-scale designs, including those at the latest technology node, 20 nanometers.
Rahul Deokar, product management director, said: “We are addressing designer challenges in – high performance design, giga-scale design and advanced node design. The first challenge is the PPA – power performance and area. Next challenge is to handle giga-scale designs with efficient turnaround time. The third key challenge is fast time-to-market on advanced 28nm/20nm design.”
With this latest release, Cadence provides the industry’s best PPA. Second, it is providing 1 billion gates on designer desktops. Third, it provides the fastest path to 20nm digital design. In the new announcement, there are three new technologies – GigaOpt + CCOpt, GigaFlex, and 20nm double patterning.
Cadence has introduced “GigaOpt” – a common optimization engine that unifies physical synthesis and optimization. GigaOpt provides designers globally optimal results across the front-end and back-end of the design flow. And that results in the benefit of the industry’s best PPA for high-performance design. GigaOpt has been designed from scratch to be multi-threaded, which makes it ultra fast and ultra scalable.
Another innovation, CCOpt, is the first and only technology in EDA to unify clock tree synthesis and physical optimization. CCOpt is now an integral part of the Encounter flow accelerating design closure with the best PPA. CCOpt facilitates:
* 10 percent improvement in design performance and total power.
* 30 percent reduction in clock power and area.
* 30 percent reduction in IR drop.
The Encounter flow now allows 1 billion gates to be enabled on the designer’s desktops. This is done with the new GigaFlex abstraction technology. It is the first and only technology in EDA that enables flexible, accurate abstraction adaptable to the flow stage. There is 10X capacity and TAT gains on 100 million+ instance designs. GigaFlex abstraction technology allows accurate, early physical modeling, concurrent top-and-block interface optimization, and concurrent hierarchical closure and late-stage ECO.
In 20nm design, geometry features are disappearing due to lithography distortion. Hence, there is a need for double patterning. The new Encounter 20nm flow employs a correct-by-construction approach that spans floorplanning and prototyping, DPT placement, DPT routing, RC extraction, physical/DFM signoff, DRC, DPT, litho, timing and power signoff.
According to Deokar, this approach results in higher die area and ECO efficiency providing the fastest path to design closure. “We are the first and only EDA vendor with an ARM Cortex A15 tapeout at 20nm. ARM, TSMC and Cadence achieved this milestone in tight and early collaboration. We are working with all key partners of the 20nm ecosystem now making sure that the infrastructure is ready for our mutual customers.”
Telecom will be the big driver in the next couple of years. It will push limits on performance, area, power, functionality, etc. Computing, and server (cloud computing) are some other areas where the industry is working on reducing power. The new Cadence Encounter RTL-to-GDSII flow is poised to help designers meet these challenges.