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Cadence Allegro 16.6 accelerates timing closure

September 26, 2012

Cadence Design Systems Inc. has released the Allegro/OrCAD 16.6 that provides unmatched, scalable design solutions addressing technology challenges.

Allegro is meant for simple to more complex boards, for the geographically dispersed design teams. They also cater to the personal productivity needs for start-ups and small to medium companies. It provides high-speed, power aware SI, HDI managed design environments, that is meant for medium to large enterprises.

Allegro, Sigrity and OrCAD – major themes of Allegro PCB 16.6
The major themes of Allegro PCB 16.6 include the first ECAD collaborative environment for work-in-progress (WiP) PCB design using Microsoft SharePoint. It accelerates the timing closure for high-speed interfaces such as DDRx. There is support for advanced miniaturization techniques that embed passive and active components on inner layers of a PCB.

Cadence Allegro is meant for simple to more complex boards.

Cadence Allegro is for simple to more complex boards.

Regarding the percentage of enhanced miniaturization capabilities for embedding dual-sided and vertical components, Hemant Shah, product marketing director, Allegro PCB and FPGA Products, Cadence, said: “Components with dual-sided contacts offer customers the ability to connect to the components pins through the layer above or through the layer below. This provides routing flexibility. It also allows customers who want redundant connections on inner layers.”

There can be accelerated design implementation through flexible PCB team design capability. Leveraging GPUs for faster display, you can pan and zoom on dense PCBs, enabling greater design productivity.

Typical product creation environment includes the best-in-class hardware design environment for implementation, analysis and compliance sign-off. The design team collaboration capability encompasses design-chain partners. Design data can be integrated into corporate systems to manage cost and quality, and provide visibility. It allows on-time release into manufacturing to build products.

Allegro, OrCAD and Sigrity ensure product creation with the best-in-class PCB design environment. Design team collaboration and productivity is integrated at the PCB. Design data integration is done into corporate systems to manage cost and quality. There is on-time release into manufacturing to build products. Allegro, OrCAD and Sigrity are helping create market leading products.

Users can create the first ECAD collaborative environment using Microsoft SharePoint. Design creation and collaboration trends include geographically distributed teams, increase in outsourcing (OEMs-ODMs), product life cycle management tools are not designed/targeted for managing work-in-progress data. For every design engineer, there are 3X-5X collaborators, reviewers, etc.

The Allegro Design workbench integrates seamlessly to SharePoint 2010. The Team Design Authoring cockpit facilitates design data in and out of SharePoint providing WiP design data management. There is block level check-in, check-out, etc. SharePoint is already deployed in many companies. It is scalable from single server to cloud environment. It has rich platform for power users to configure and developers to customize.

By creating the first ECAD collaborative environment, users can reduce the product creation time by up to 40 per cent. Chances of first pass failure are also reduced from 25 per cent to 1 per cent. Users can accelerate the timing closure on high-speed, multi-Gigabit signals.

Auto-interactive delay tune feature
One feature is the auto-interactive delay tune (AiDT). By selecting a set of routed signals, AiDT adjusts timing of signals to meet the constraints. It also shortens time to tune high-speed signals by 30-50 per cent.

How does the AiDT assist in physical implementation? According to Shah, AiDT assists in getting the high-speed signals tuned for meeting timing requirements. It automates addition of tuning to a group of signals. It eliminates the need to do tuning manually on a single trace at a time.

EMA’s TimingDesigner is the industry standard for graphical static timing analysis over a broad range of interface analysis applications. TimingDesigner’s diagrams and spreadsheet technology allows the modeling of unique timing challenges and there is visibility of internal signal relationships. Users can easily manage the increasingly tighter critical path timing margins of high-speed interface designs.

Advanced miniaturization techniques are also supported. Embedded components were first supported in 16.5 release (June 2011). This release supports advanced techniques requested by customers, such as dual-sided components, vertical components and support for embedding in dielectric on two-layer boards.

Partnerships with AT&S, NVIDIA
Cadence has partnered with AT&S since 2010 to support advanced techniques. Customers can ‘miniaturize’ end product footprints using these advanced techniques to embed components. They can develop differentiated products faster.

Allegro has streamlined PCB team design option. There is an increased flexibility for PCB designers. Components can be moved or routed across  partition boundaries. Constraints, such as electrical, physical and spacing can be edited inside a partition. It reduces the need to merge-and-split often. There is a 2x-3x performance improvement in time to merge partitions into master.

The new wizard automates steps involved with ECO changes coming from the front end, so time is saved to merge-and-split. Time to create PCB designs is shortened as well.

Cadence has collaborated with NVIDIA to improve display performance. There is significant display performance improvement. Optimized OpenGL code has been moved to the GPU, hence, taking burden off of the CPU. Cadence and NVIDIA engineers collaborated to improve the display performance. There is a 4X improvement on Quadro 2000 GPUs and 5.6X improvement on Quadro 5000 GPUs.

“With our design complexity increasing, the hardware struggles to provide the productivity designers expect.  We partnered with Cadence to optimize Allegro’s use of OpenGL graphics on hardware equipped with NVIDIA Quadro GPU’s,” said Greg Bodi, director, Systems Design, NVIDIA. “Allegro 16.6 improves our efficiency by removing the latency that was common on dynamic shape adherence to our design rules.”

OrCAD 16.6 release goals
The Cadence OrCAD 16.6 release goals include multi-core support for PSpice, capture signal integrity flow and Tcl integration for PSpice.

In multi-core support for PSpice, customers are expecting performance gains from modern, multi-core hardware. Performance enhancements are done through algorithm/engine optimizations and multi-core support. It is focused on the large designs and/or designs with complex model instances (MOSFETs, BJTs).

Metrics are confirmed on customer circuits. There is an average of 20 per cent reduction in simulation time. Target designs achieve the biggest improvements, up to 65 per cent reduction.

For capturing signal integrity flow, the pre-layout SI circuit exploration requires manual process to define in signal integrity tool. There is direct integration/data flow between OrCAD Capture and OrCAD PCB SI. This process replicates selected circuits as signal integrity topologies for pre-layout topology exploration, analysis, and constraint development. Lastly, it accelerates and automates the previous manual process and preserves data throughout the design flow.

The Tcl integration for PSpice includes the fulfillment of pent-up demand or requirements through custom programming. There is new capability to customize and extend simulation environment, giving access to simulation data, parameters, and simulator. It enables custom or enhanced features/functions and design capabilities.

Tcl-driven simulation opportunities include multiple analysis on simulation netlist. The schematic variables in analysis Tcl equations, temperatures, tolerances, etc., pre-defined algorithms or user-defined analysis. Analysis output from probe/user-defined plots/post-processing is also available.

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  1. zainfr2012
    September 26, 2012 at 10:53 am

    Thanks for report!

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