Home > EDA, EDA Consortium, EDA industry, EDA products, global semiconductor industry, global semiconductor market, Mentor Graphics, Walden C. Rhines > Next wave of design challenges, and future growth of EDA: Dr. Wally Rhines

Next wave of design challenges, and future growth of EDA: Dr. Wally Rhines

December 15, 2012

Dr. Wally Rhines.

Dr. Wally Rhines.

Today, EDA requires specialization. Elaborating on EDA over the past decade, Dr. Walden (Wally) C. Rhines, chairman and CEO, of Mentor Graphics, and vice chairman of the EDA Consortium, USA, said that PCB design has been flat despite growth in analysis, DFM and new emerging markets. Front end design has seen growth from RF/analog design and simulation, and analysis As design methodologies mature, EDA expenditures stop growing. He was speaking at Mentor Graphics’ U2U (User2User) conference in Bangalore, India.

Most of the EDA revenue growth comes from major new design methodologies, such as ESL, DFM, analog-mixed signal and RF. PCB design trend continues to be flat, and includes license and maintenance. The IC layout verification market is pointing to a 2.1 percent CAGR at the end of 2011. The RTL simulation market has been growing at 1.3 percent CAGR for the last decade. The IC physical implementation market has been growing at 3,4 percent CAGR for the last decade.

Growth areas in EDA from 2000-2011 include DFM at 28 percent CAGR, formal verification at 12 percent, ESL at 11 pecent, and IC/ASIC analysis at 9 percent, respectively.

What will generate the next wave of electronic product design challenges, and the future growth of EDA? This would involve solving new problems that are not part of the traditional EDA, and ‘do what others don’t do!

Methodology changes that may change EDA
There are five factors that can make this happen. These are:
* Low power design beyond RTL (and even ESL).
* Functional verification beyond simulation.
* Physical verification beyond design for manufacturability.
* Design for test beyond compression.
* System design beyond PCBs

Low power design at higher levels
Power affects every design stage. Sometimes, designing for low power at system level is required. System level optimization has the biggest impact on power/performance. And, embedded software is a major point of leverage.

Embedded software has an increasing share of the design effort. Here, Mentor’s Nucleus power management framework is key. It has an unique API for power management, enables software engineers to optimize power consumption, and reduces lines of application code. Also, power aware design optimizes code efficiency.

Functional verification beyond RTL simulation
The Verification methodology standards war is over. UVM is expected to grow by 286 percent in the next 12 months. Mentor Graphics Questa inFact is the industry’s most advanced testbench automation solution. It enables Testbench re-use and accelerates time-to-coverage. Intelligent test bench facilitates linear transition to multi-processing.

Questa accelerates the hardware/software verification environment. In-circuit emulation has been evolving to virtual hardware acceleration and embedded software development. Offline debug increases development productivity. A four-hour on-emulator software debug session drops to 30 minutes batch run. The offline debug allows 150 software designers to jumpstart debug process on source code. Virtual stimulus increases the flexibility of the emulator. As an example, Veloce is 700x more efficient than large simulation farms.

Physical verification beyond design for manufacturability
The Calibre PERC is a new approach to circuit verification. The Calibre 3DSTACK is the verification flow for 3D.

Design for test beyond compression
There are certain parameters. These include:

Next generation logic test
* Seamless integration of BIST and compression.
* New introspection-based insertion methodology.
* Auto test point insertion for low coverage logic.
* A new level of possible compression.

Hierarchical test
* Managing 100 million gate complexity.
* Multi-core broadcast capability.
* Core-level pattern re-use.
* Eliminates performance and capacity bottlenecks.

3D IC testing
* MemoryBIST on SoC for DRAM and interface.
* BoundaryScan for digital and AC coupled I/O.
* Tessent Serdes for high-speed interfaces.
* TestKompress and LogicBIST for KGD and in-situ logic test.

Cell-aware ATPG – next level in test quality
* Unique detections and PPM quality improvement using cell-aware test patterns.
* Major improvement in test quality.
* Significant reduction in costly functional test.

System design beyond PCBs
There are discontinuities in traditional EDA — ESL. Mentor Graphics has extended system design into full flow including manufacturing with VALOR. For new EDA problems that lie out-of-the-box, there is a need to find new problems for existing capabilities, and acquiring new or related capabilities.

Thermal management is important, in terms of package thermal boundary conditions. Package and IC geometry are used to determine 3D-IC thermal compliance. An example: Designing the ultimate beer fridge with FloTHERM, or using Flowmaster for modeling in-flight refueling. This, is Mentor Graphics’ journey to anticipate and solve new problems before they become problems!

Advertisements
  1. Suzan Kawaguchi
    January 6, 2013 at 10:51 pm

    Hello there. I found your blog using MSN. This is a really well written article. I will make sure to bookmark it and come back to read more of your useful information. Thanks for the post. I’ll definitely come back.

  1. No trackbacks yet.
Comments are closed.
%d bloggers like this: