Synopsys on outlook for global semicon 2013!

January 17, 2013

Thanks to Sheryl Gulizia, senior manager, Worldwide Public Relations, Synopsys Inc., I was able to connect with John Chilton, senior VP of Marketing and Strategic Development, Synopsys. We discussed the global (and Indian) outlook for the semiconductor industry in detail. Dr. Aart De Geus was apparently away on a business meet. 

John Chilton.

John Chilton.

According to Chilton, the semiconductor industry has repeatedly stared down the daunting technical challenges caused by the necessity of Moore’s Law and the inevitability of the laws of physics. Every time, the industry has risen to the challenge and delivered silicon that is smaller, faster and cheaper, and the design and systems companies that were quickest to exploit the new technologies reaped the great benefit.

Power dissipation challenging
One trend that has proven to be especially challenging is power dissipation. Although transistors get smaller, faster and cheaper, chip power keeps increasing. Increasing power and decreasing size could have caused device-melting energy densities, but the industry rose to the challenge with more innovative physics along with smarter design methods and tools.

This time around, the challenge seems more fundamental, with the new nodes offering either better performance or lower power, but not both at the same time, and maybe not at a lower cost. The fundamental driving factor behind innovation has been smaller, faster and cheaper transistors, with the cheaper part making the migration a no-brainer. Unfortunately, this time the new node is not expected to be cheaper.

App processors to drive move to 20nm
Application processors for mobile and cloud-based services will drive the move to 20nm. These applications have the volume and power/performance needs to justify the expected investment required to embrace the 20nm node. Recent product announcements at CES underscore the emergence of the ‘cloud to mobile client’ trend in consumer electronics.

Dell and Wyse unveiled the project Ophelia. Ophelia is a USB memory stick-sized thin client that will plug into any compatible TV or Dell monitor. The device will boot into an Android OS and turn any TV into a portal to access a computer somewhere else. Ophelia works by taking advantage of the MHL protocol and works with any MHL-enabled display. Over 100-million MHL-compliant chipsets have already been shipped, so the opportunities for this type of interaction are growing.

MHL, along with established standards such as USB and HDMI or even future short-range wireless standards, will enable consumers to plug their cell phone into any monitor or TV and consume content via their phone on a larger, more satisfying display.

Coincidentally, on the same day, Samsung announced consumer displays that utilize voice and gesture recognition. These emerging technologies will begin to redefine the way we interact with the cloud. Instead of carrying a laptop, you may end up waving and talking to a TV. In a futuristic presentation, Lexus showed a prototype of a laser-scanning system that is small enough to be mounted on a grill and makes 3-D maps of the environment surrounding a car. This kind of embedded vision technology will make its way into more devices as processor performance increases.

Chilton said that developing such complex systems and applications require a robust verification solution. Chip designers already use complex and exhaustive test benches to test individual blocks and subsystems. Verification engineers will need to move up to the next level and handle the full verification of the SoC within a target system.

Verification of an integrated system will require an integrated verification solution that includes not just simulation but also acceleration, emulation and formal debug. A new, integrated verification platform should combine these existing discrete technologies to offer the productivity needed to realize complex systems with predictable, manageable schedules.

Delivering the hardware simultaneously with a working OS and development kit will require virtual prototypes, which will be used by software developers prior to the release of working hardware.

EUV lithography’s future
As per John Chilton, one thing we will not see in 2013 is the introduction of extreme ultraviolet (EUV) lithography. This manufacturing technique has been in development for some time and was not a viable option for 20nm. At 20nm, we will have to rely on double patterning techniques that use additional masks in the manufacturing process. EDA tools must handle this from place and route all the way down to mask synthesis tools.

FinFETs are the clearest way to deliver the benefits of smaller, faster and cooler in 2013. Another great way to reduce power is simply to lower the threshold voltage. Unfortunately, reducing the threshold voltage also increases problems due to on-chip variation, signal integrity issues, and power reliability. Better, tightly integrated EDA tools will enable designers to make more precise trade-offs when they model voltage-related issues so that threshold voltages can be lowered while keeping the physical impact under control.

The requirements of 20nm will increase the need for physical awareness across the design flow. A single, integrated implementation platform will be necessary, giving different parts of the flow visibility across traditional tool boundaries. The place and route system must be aware of manufacturing constraints or design-rule limitations. ECOs will not only need to be correct before physical verification, but they also will need to be incrementally limited to just the affected region.

RTL designers should be able to use physical constraints to produce results that will seed place and route tools. Conversely, the placer or route tool should be able to provide more detailed physical results that can be used to synthesize more efficient logic. The ultimate goals should be an implementation that is correct by construction.

What about India?
Synopsys envisions a positive trend for the Indian semiconductor industry in 2013. Although India will continue to grow with the worldwide semiconductor industry, it is important to note the impact of the National Policy on Electronics (NPE) launched by the Department of Electronics and Information Technology.

There are four specific initiatives that will foster growth in the Indian semiconductor industry. These initiatives are:
* Modified Special Incentive Package Scheme (M-SIPS)
* Electronics Manufacturing Cluster (EMC)
* Preference to Domestically Manufactured Electronic Goods
* Electronic Development Fund.

Coupled with organic growth in R&D, these initiatives should boost spending within the Electronics System Design and Manufacturing (ESDM) sector. All drivers point to an even closer collaboration between the EDA industry, foundries and design teams to deliver working flows that span the range from initial design all the way through to manufacturing, test and packaging.

  1. Rzeszów
    February 1, 2013 at 9:47 am

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