Xilinx targets growing ASIC and ASSP gaps

March 19, 2013

Xilinx Inc. has announced solutions for significant and growing gaps in ASIC and ASSP offerings targeting next-generation smarter networks and data centers. It has been acquiring and developing a SmartCORE IP portfolio and a critical mass of application specialists and services that leverage Xilinx’s All Programmable FPGAs, SoCs, and 3D ICs.

Neeraj Varma

Neeraj Varma.

To find out more about how are Xilinx’s solutions targeting growing ASIC and ASSP gaps for next-gen smarter networks and data centers, I spoke with Neeraj Varma, director, Sales-India, Xilinx. He said: “Over the past several years, Xilinx has been making a transition from the leading FPGA vendor to a provider of All Programmable Solutions for Smarter Systems. With its All Programmable 7 Series FPGAS, All Programmable SoCs and the VivadoTM Design Suite, Xilinx now offers a comprehensive set of solutions that provide end-to-end system implementation.

“Through strategic acquisitions, investments in silicon products and IP development, Xilinx has started to replace entire ASSPs and ASICs in the communications market by offering a complete IP cores portfolio which allows customers to design Smarter Systems for networking, communications and data center applications.

“Xilinx is calling this set of IP cores, SmartCORE IP, because they are the critical application-specific building blocks needed to develop smarter networking and communications systems. We are responding to market need and that need has accelerated recently as the viability of ASICs and more recently ASSPs have been severely challenged. Xilinx is a generation ahead in SoC and tools and its leadership at 28nm borne out with revenue ramp.”

Developing SmartCORE IP portfolio
What is meant by Xilinx acquiring and developing a SmartCORE IP portfolio and a critical mass of application specialists and services?

According to him, 28nm design process devices require a new and a different set of tools to exploit all the capabilities. That was one of the reasons for Xilinx to invest heavily in resources and time to come up with the Vivado Design Suite, to be able to support the large designs and get them into production with minimal effort and ease.

Vivado supports the growing use of IP blocks to reduce the complexity of the designs which are very critical in the implementation of complex networking and communications systems. This is one of the main reasons Xilinx spent years to develop strategic partnerships and making acquisitions such as Omiino (OTN IP solutions), Modelware (Traffic Management and Packet processing IP solutions), Sarance (Ethernet and Interlaken IP solutions) and Modesat (Microwave and Eband backhaul IP solutions) to offer a comprehensive set of IP cores to design Smarter Systems for networking, communications and data centre applications.

How are the solutions going to address the challenges with ASICs and ASSPs?

He said that ASICs and ASSPs targeting the communications, networking, and data center equipment markets have been disappearing at a surprisingly rapid pace due to many factors, including escalating IC-design costs and the need for much greater levels of intelligence and adaptability—all driven by wide variance in application and device requirements.

Additionally, the equipment markets no longer accept “me too” equipment design, which means that ASSP-based equipment design has almost vanished due to limited flexibility. These growing gaps are pervasive across all markets.These challenges, coupled with the rapidly increasing design costs and lengthy design cycles for both ASICs and ASSPs have created significant solution gaps for equipment design teams.

ASSPs and ASICs are either too late to market to meet OEM or operator requirements, are significantly overdesigned to satisfy the superset requirements of many diverse customers, are not a good fit for specific target applications, and/or provide limited ability for customers to differentiate their end products. Equipment vendors face many or all of these gaps when attempting to use the solutions offered by ASIC and ASSP vendors.

The biggest driver in the communications and networking markets is the insatiable need for bandwidth as traffic explodes well beyond the capabilities of networks to support that traffic.  However, the need is definitely not bandwidth or transmission capacity at any cost. It’s really a need for more bandwidth and more capacity at lower and lower cost in both wireless and wired networks.

The only way to reduce the costs associated with bandwidth or capacity is to make the systems that deliver that bandwidth more intelligent, to include:

* The ability to eke more bandwidth from the same transmission medium while meeting quality-of-services requirements.
* The ability to forge heterogeneous wireless or wired networks and data centers into a seamless bandwidth delivery system.
* The ability to efficiently and quickly adapt to changes in network configuration, network usage, and market requirements.

All of these abilities require multiple forms of programmability. For example, cellular services providers need to reconfigure their base stations as new and better algorithms are introduced and would prefer to avoid a truck roll to accommodate these changes. Data center managers need ways to quickly provision for new usage patterns without having to send a person walking down an aisle to change patch cords or install new network appliances in every fourth rack in the building.

Xilinx calls this need for programmability the “programmable imperative.” No networking or communications system, no Smarter Network from this point forward can be designed without multiple forms of embedded programmability because doing so guarantees quick obsolescence and shortened end-product life.

Further, Xilinx believes that the programmable imperative is as much a mandate for Xilinx as it is for the company’s networking and communications customers, which is one of the key reasons behind the development of the company’s 28nm portfolio.

Xilinx All Programmable portfolio enables designers to bring value in both hardware (digital and analog) and software through the creation of customized and highly integrated designs.

Building smarter systems
Finally, how can SmartCORE IP-based solutions help build smarter systems?

Xilinx Vivado Design Suite supports the growing use of IP blocks – because no design team can or even wishes to design every block of complex design. For example, there’s no added value in designing yet another Ethernet controller or PCIe interface, while there is tremendous value in incorporating such blocks in a system-level design.

Such elements are now handled as pre-designed, pre-verified, proven IP blocks. These blocks are critical to the design and implementation of complex networking and communications systems, which is why Xilinx has spent the past several years investing in strategic acquisitions and partnerships – to bring critical IP in house so that system vendors can develop their designs with Xilinx All Programmable Solutions.

SmartCORE IP-based solutions include a rich set of IP and associated design expertise to tackle the existing challenges of ever-increasing demand of bandwidth while lowering the cost.

Through years of strategic acquisitions and internally developed technology, Xilinx is in a position to deliver solutions to address these challenges through a combination of All Programmable, Generation ahead silicon like FPGAs, 3D ICs and SoCs along with domain specific IP and expertise. Xilinx solutions are targeted towards three market segments, Smarter Wireless HetNets, Smarter Wired Networks and Smarter Data Centers.

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