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How’s global semicon industry performing in sub-20nm era?

December 22, 2013

Early this month, I caught up with Jaswnder Ahuja, corporate VP and MD, Cadence Desiign Systems India. With the global semiconductor industry having entered the sub-20nm era, there are a lot of things happening, and Cadence is sure to be present.

Performance in sub-2onm era
First, let’s see how’s the global semiconductor industry performing after entering the sub-20nm era.

Jaswinder Ahuja

Jaswinder Ahuja

Ahuja replied: “Increased demand for faster, smaller, low-power chips continues to drive the geometry shrink as one of the ways to manage the low-power, higher performance goals in smaller form factors—in other words, PPA is driving the move to advanced node design.

“At Cadence, we are seeing a lot of interest in the wireless space, which includes smartphones, tablets, and consumer devices. In this market, you must support different standards, the device must be really fast, it must have Internet access, and all this must be done at lower power so the that it does not drain the battery. We’re also seeing interest for advanced nodes in other segments such as computing and graphics processors.”

When speaking of advanced nodes, let’s also try and find out what Cadence is doing in helping achieve 10X faster power integrity analysis and signoff.

Cadence Voltus IC power integrity Solution is a full-chip, cell-level power signoff tool that provides accurate, fast, and high-capacity analysis and optimization technologies to designers for debugging, verifying, and fixing IC chip power consumption, IR drop, and electromigration (EM) constraints and violations.

The Voltus solution includes innovative technologies such as massively parallel execution, hierarchical architecture, and physically aware power grid analysis and optimization. Beneficial as a standalone power signoff tool, Voltus IC Power Integrity Solution delivers even more significant productivity gains when used in a highly integrated flow with other key Cadence products, providing the industry’s fastest design closure technology.

Developed with advanced algorithms and a new power integrity analysis engine with massively parallel execution, Voltus IC Power Integrity solution:
* Performs 10X faster than other solutions on the market.
* Supports very large designs—up to one billion instances—with its hierarchical architecture.
* Delivers SPICE-level accuracy.
* Enhances physical implementation quality via physically aware power integrity optimization.

Supported by major foundries and intellectual property (IP) providers, Voltus IC Power Integrity Solution has been validated and certified on advanced nodes processes such as 16nm FinFET and included in reference design flows such as for 3D-IC technology. Backed by Cadence’s rigorous quality control and product release procedures, the Voltus solution delivers best-in-class signoff quality on accuracy and stability for all process nodes and design technologies.

FinFETs to 20nm – are folks benefiting?
It is common news that FinFETs have gone to 20nm and perhaps, lower. Therefore, are those folks looking for power reduction now benefiting?

Ahuja replied that FinFETs allow semiconductor and systems companies to continue to develop commercially viable chips for the mobile devices that are dominating the consumer market. FinFETs enable new generations of high-density, high-performance, and ultra-low-power systems on chip (SoCs) for future smart phones, tablets, and other advanced mobile devices. Anyone who adopts FinFET technology will reap the benefits.

Foundry support for FinFETs will begin at 16nm and 14nm. In April of this year, Cadence announced a collaboration with ARM to implement the industry’s first ARM Cortex-A57 processor on TSMC’s 16nm FinFET manufacturing process. At ARM TechCon 2012, Cadence announced a 14nm test chip tapeout using an ARM Cortex-M0 processor and IBM’s FinFET process technology.

Meeting design challenges at 20nm
We will also check out how’s Cadence meeting the design challenges at 20nm, with respect to the need for double patterning, to overcome the limits of existing lithography equipment.

Ahuja noted that there are several challenges associated with double patterning. Double patterning impacts cell and library generation. You must make sure silicon intellectual property (IP) is compliant with double patterning layout rules. It is also critical to account for double patterning during placement.

Cadence’s unique technology performs automatic colorized placement, with the end benefit being a less congested design. With less congestion, it is much easier to meet timing and power requirements.

What about double patterning?
The biggest impact of double patterning is in routing. The double patterning must be integrated inside the routing solution—it cannot be an afterthought where you finish the routing and then run decomposition. It must be correct-by-construction.

Cadence’s approach is to carry double patterning intent forward, from cell and IP generation to double-pattern aware routing, and finally, to signoff physical verification. This approach provides faster convergence because intent is carried forward throughout the flow. A second benefit is better quality of results.

Challenges like double patterning, clock design, and layout-dependent effects all must be considered up front in the design flow, from IP characterization to placement and routing and final signoff. To confront these challenges, an end-to-end flow is required, and that is what Cadence offers.

So, what is Cadence doing in 20nm that involves in-design physical verification throughout the flow to reduce time-consuming, uncertain iterations?

In-design physical verification is becoming more complex at advanced nodes when designs are bigger and the number and complexity of DRC rules are more. Ensuring a DRC clean design while still meeting the tapeout window is a challenge.

Proven on many successful production tapeouts in nanometer process technologies, Cadence Physical Verification System is the premier Cadence signoff solution enabling in-design and back-end physical verification, constraint validation, and reliability checking.

Recently PMC adopted the Cadence Physical Verification System as the signoff technology for its global design centers. PMC has used the Physical Verification System for several successful tapeouts, including PMC’s DIGI 120, described as the industry’s only single-chip processor supporting 10G, 40G, and 100G speeds for OTN transport, aggregation, and switching. The device, with 200+ million gates and 180+ Mbits of RAM, is the largest production SoC that PMC has delivered.

Early RTL and design explorations
Next, it would be interesting to see how Cadence has been handling the early RTL and design explorations.

Ahuja said that accommodating today’s chip design requirements within narrow market windows has led to a predictability crisis. How can engineers determine design feasibility for larger, higher performance, power-hungry chips with an incomplete netlist, library, and constraints? And, how can they quickly assess floorplans for congestion, timing, and power without having to go into real implementation?

Cadence provides two solutions. The first is Cadence First Encounter Design Exploration and Prototyping technology. First Encounter offers a comprehensive flat and hierarchical design planning, analysis, and debug environment for complex designs. Its GigaFlex technology adapts to growing capacity requirements while still retaining the relevant timing, placement, and congestion information to accurately plan and implement 100M+ instance designs.

The latest advanced node and low-power capabilities make hierarchical implementation of high-speed and advanced-node designs faster and easier, which in turn produces designs that consume lower power. In addition, with unique partitioning and budgeting capabilities, First Encounter technology ensures convergence and provides a predictable path to design closure.

The second solution is Cadence InCyte Chip Estimator. Incyte enables rapid and accurate early chip planning. Fast “what-if” estimation of size, performance, power, and cost enables early exploration of functional content, IP components, memories, and process technology with foresight into the technical and business consequences of these decisions. InCyte Chip Estimator helps chip design projects start and stay on track toward their technical and business goals.

Status of 3D ICs
Finally, what’s the status with 3D ICs? How is Cadence helping with true 3D stacking integration?

Performance and area real estate have been driving the vertical dimension for several years. 3D IC packages pack heterogeneous die—logic, memory, RF, MEMs—at different process nodes to create different solutions. Micron is bullish on its Hybrid Memory Cube technology. SK Hynix, Fujitsu, Samsung, and others are said to have technologies in the works. TSMC, GlobalFoundries, and others have 2.5D offerings for customers.

From a design standpoint, extensive retooling is not needed for 3D ICs. Cadence offers a comprehensive solution to support the 3D IC revolution, including analog and digital implementation, packaging, and printed circuit board (PCB) design tools. And there are no apparent showstoppers in process technology.

Ahuja noted that in September 2013, Cadence announced its partnership with TSMC to develop a 3D-IC reference flow featuring innovative true 3D stacking. The flow, validated on a memory-on-logic design with a 3D stack based on a Wide I/O interface, enables multiple die integration, incorporating TSMC 3D stacking technology and Cadence solutions for 3D-IC, including integrated planning tools, a flexible implementation platform, and signoff and electrical/thermal analysis

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