FinFETs delivering on promise of power reduction: Synopsys

February 1, 2014

Here is the concluding part of my conversation with Synopsys’ Rich Goldman on the global semiconductor industry.

Rich Goldman

Rich Goldman

Global semicon in sub 20nm era
How is the global semicon industry performing after entering the sub 20nm era? Rich Goldman, VP, corporate marketing and strategic alliances, Synopsys, said that driving the fastest pace of change in the history of mankind is not for the faint of heart. Keeping up with Moore’s Law has always required significant investment and ingenuity.

“The sub-20nm era brings additional challenges in device structures (namely FinFETs), materials and methodologies. As costs rise, a dwindling number of semiconductor companies can afford to build fabs at the leading edge. Those thriving include foundries, which spread capital expenses over the revenue from many customers, and fabless companies, which leverage foundries’ capital investment rather than risking their own. Thriving, leading-edge IDMs are now the exception.

“Semiconductor companies focused on mobile and the Internet of Things are also thriving as their market quickly expands. Semiconductor companies who dominate their space in such segments as automotive, mil/aero and medical are also doing quite well, while non-leaders find rough waters.”

Performance of FinFETs
Have FinFETs gone to below 20nm? Also, are those looking for power reduction now benefiting?

He added that 20nm was a pivotal point in advanced process development. The 20nm process node’s new set of challenges, including double patterning and very leaky transistors due to short channel effects, negated the benefits of transistor scaling.

To further complicate matters, the migration from 28nm to 20nm lacked the performance and area gains seen with prior generations, making it economically questionable. While planar FET may be nearing the end of its scalable lifespan at 20nm, FinFETs provide a viable alternative for advanced processes at emerging nodes.

The industry’s experience with 20nm paved the way for an easier FinFET transition. FinFET processes are in production today, and many IC design companies are rapidly moving to manufacture their devices on the emerging 16nm and 14nm FinFET-based process geometries due to the compelling power and performance benefits. Numerous test chips have taped out, and results are coming in.

“FinFET is delivering on its promise of power reduction. With 20nm planar FET technologies, leakage current can flow across the channel between the source and the drain, making it very difficult to completely turn the transistor off. FinFETs provide better channel control, allowing very little current to leak when the device is in the “off” state. This enables the use of lower threshold voltages, resulting in better power and performance. FinFET devices also operate at a lower nominal voltage supply, significantly improving dynamic power.”

Next, how can folks save closure time and boost performance by incorporating knowledge of physically aware design early into your front-end design implementation flow? He added that this is an area that Synopsys has invested in heavily over the years and one where we offer industry-best solutions.

“Our top-of-the line synthesis offering, Design Compiler Graphical, was driven by this exact need. Design Compiler Graphical shares placement technology with our market-leading place and route product, IC Compiler, bringing physically aware design consideration to the front end. Design Compiler Graphical enables physically aware timing/area/power optimization, and is able to detect and resolve areas of high congestion and improve overall time to close the design.”

Status with 3D ICs
What’s the status with 3D ICs? How is Synopsys helping with true 3D stacking integration?

He added: “For several years, Synopsys has been collaborating with design and foundry partners who are researching advanced, multi-die packaging concepts, including “2.5D” silicon interposer-based and “3D-IC” vertical stacked die systems. Through this collaboration, an evolutionary transition from 2D- to 3D-IC integration has been devised and successfully demonstrated.

“Synopsys implementation, simulation and verification tools have been enhanced specifically to address 3D-IC designs. The ecosystem is in place, and multiple, foundry-certified design flows are now available.

“Our existing design tools are now upgraded to enable 2.5D and 3D-IC design. For example, Synopsys has delivered: a new 45-degree redistribution layer (RDL) router for silicon interposer design; support for 3D structures, such as through-silicon vias (TSV) and micro-bumps, in our place and route, parasitic extraction, and physical verification tools; and multi-technology support in our SPICE simulation, static timing analysis and physical verification tools.”

3D-IC design is actively underway at many leading semiconductor design companies across the globe. There are several commercial examples already in production in the FPGA, memory and CMOS image sensor markets with more to come. As with other advanced design and manufacturing technologies, the road for 3D-IC is long and will co-exist with other related technologies that form part of the multi-dimensional toolbox that design companies utilize in providing faster, smaller, cheaper, smarter electronic systems to their consumers.

What is Synopsys doing in helping achieve 10X faster power integrity analysis and signoff?

Power integrity is a critical concern for advanced system-on-chip (SoC) designs, especially those targeting high-growth mobile and wireless applications. Each new generation of process technology allows more performance and functionality to be packed into a smaller area. However the increasing demand for lower power and increased battery life are increasing the complexity significantly.

In particular, designing a robust power network to work reliably across several operational modes of a design has emerged as a key challenge. Designers are spending considerable time analyzing and debugging their power network design post-physical implementation. They are demanding increased productivity and faster turnaround time (TAT) to meet tapeout schedules.

However, in order to achieve 10X or faster TAT, a comprehensive solution is needed that not only provides faster runtime performance but also includes methodology allowing designers to perform early and frequent checks to ensure integrity of their power network throughout the physical implementation process. Such a comprehensive solution provides the biggest bang for the buck in TAT through early intervention and avoidance of late-stage surprises close to tapeout.

Goldman added: “Synopsys is leading the industry by integrating its PrimeRail power integrity analysis and signoff solution in the IC Compiler physical implementation system for In-Design analysis to accelerate design closure and signoff TAT. The In-Design rail analysis utilizes PrimeRail’s advanced analysis and guidance technology to enable designers to easily perform power integrity analysis from within the physical implementation environment at any stage.

“Also, PrimeRail is built on Synopsys’ gold standard PrimeTime and PrimeTime PX timing and power analysis solutions, offering the unique advantages of proven infrastructure and trusted accuracy needed for large-scale advanced node designs. In addition, PrimeRail’s efficient multi-core architecture provides enhanced flexibility to adapt to designers’ evolving compute resource environments to meet their increasing performance/TAT needs.

Finally, how is Synopsys meeting the design challenges at 20nm with respect to the need for double patterning to overcome the limits of existing lithography equipment?

Goldman said: “Double patterning (DPT) is a major discontinuity at 20nm, but this is not unanticipated. We started working with our manufacturing partners years in advance, and today DPT is largely behind us. We are fielding highly efficient solutions in our implementation and manufacturing toolsets, which honor DPT with low overhead.

“In implementation, IC Compiler produces a DP-compliant layout generated to foundry specification, and IC Validator is used to provide signoff-quality verification. Downstream, our mask synthesis solution, Proteus, can be used to decompose the layout into alternating masks.”

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