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Accelerating EDA innovation through SoC design methodology convergence

September 26, 2014 Comments off

According to Dr. Walden C. Rhines, chairman and CEO, Mentor Graphics Corp., verification has to improve and change every year just to keep up with the rapidly changing semiconductor technology. Fortunately, the innovations are running ahead of the technology and there are no fundamental reasons why we cannot adequately verify the most complex chips and systems of the future. He was speaking at the recently held DVCON 2014 in Bangalore, India.

DVCON India 2014.

DVCON India 2014.

A design engineer’s project time for doing design has reduced by 15 percent from 2007-2014, while the engineer’s time for doing verification had seen 17 percent increase during the same time. At this rate, in about 40 years, all of a designer’s time will be devoted to verification. At the current rate, there is almost no chance of getting a single-gate design correct on first pass!

Looking at a crossover of verification engineers vs. designer engineers, there is a CAGR designers of 4.55 percent, and for CAGR verifiers, it is 12.62 percent.

The on-time completion remains constant, as we look at the non-FPGA project’s schedule completion trends, which are: 67 percent behind schedule for 2007, 66 percent behind schedule for 2010, 67 percent behind schedule for 2012, and 59 percent behind schedule for 2014. There has been an increase in the average number of embedded processors per design size, moving from 1.12 to 4.05.

Macro trends
Looking at the macro trends, there has been standardization of verification languages. SystemVerilog is the only verification language growing. Now, interestingly, India leads the world in SystemVerilog adoption. It is also remarkable that the industry converged on IEEE 1800. SystemVerilog is now mainstream.

There has been standardization in base class libraries as well. There was 56 percent UVM growth between 2012 and 2014, and 13 percent is projected growth in UVM the next year. Again, India leads the world in UVM adoption.

The second macro trend is standardization of the SoC verification flow. It is emerging from ad hoc approaches to systematic processes. The verification paradox is: a good verification process lets you get the most out of best-in-class verification tools.

The goal of unit-level checking is to verify that the functionality is correct for each IP, while achieving high coverage. Use of advanced verification techniques has also increased from 2007 to 2014.

Next, the goal of connectivity checking is to ensure that the IP blocks are connected correctly, a common goal with IP integration and data path checking.

The goal of system-level checking is performance, power analysis and  SoC functionality. Also, there are SoC ‘features’ that need to be verified.

A third macro trend is the coverage and power across all aspects of verification. The Unified Coverage Interoperability Standard or UCIS standard was announced at DAC 2012 by Accellera. Standards accelerate the EDA innovation!

The fourth trend is active power management. Now, low-power design requires multiple verification approaches. Trends in power management verification include things like Hypervisor/OS control of power management, application-level power management, operation in each system power state, interactions between power domains, hardware power control sequence generation, transitions between system power states, power domain state reset/restoration, and power domain power down/power up.

Macro enablers in verification
Looking at the macro enablers in verification, there is the intelligent test bench, multi-engine verification platforms, and application-specific formal. The intelligent test bench technology accelerates coverage closure. It has also seen the emergence of intelligent software driven verification.

Embedded software headcount surges with every node. Clock speed scaling slows the simulation performance improvement. Growing at over 30 percent CAGR from 2010-14, emulation is the fastest growing segment of EDA.

As for system-level checking, as the design sizes increase emulation up, the FPGA prototyping goes down. The modern emulation performance nmakes virtual debug fast. Virtual stimulus makes emulator a server, and moves the emulator from the lab to the datacenter, thereby delivering more productivity, flexibility, and reliability. Effective 100MHz embedded software debug makes virtual prototype behave like real silicon. Now, integrated simulation/emulation/software verification environments have emerged.

Lastly, for application-specific formal, the larger designs use more formal. The application-specific formal includes checking clock domain crossings.

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SEMICON Europa 2014 calls for innovators

September 16, 2014 1 comment

SEMICON Europa 2014 will be held at Grenoble, France, on October 7-9 October, 2014. The event will see over 400 exhibitors, which means, the exhibition area has expanded by over 40 percent vs. 2013. There will be over 70 programs featuring 300+ speakers. SEMI expects 6,000+ visitors.

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A feature of the event will be the Innovation Village that will feature 35 start-ups. I have been just informed that four start-ups have cancelled. So, that leaves 31 start-ups: ActLight, Aryballe, Avalun, Bluwireless Technology, CALAO Systems, Enerstone, Euresis, Epigan, Evaderis, Exagan, Feeligreen, Genes’Ink, Grapheat, Gridbee, Heyday, Hotblock Onboard, Imagsa Technology, Irlynx, Madci, Metablue Solution, Nessos, Nocilis Materials, Noivion, PETsys Electronics, Pollen Technology, Scint-X, Sepcell, Silicon Line GmbH, Smoltek, Sol Voltaics and Wavelens.

A few start-ups are given below:

ActLight SA: It focuses in the field of CMOS photonics.

AVALUN SAS: It currently develops the LabPad®, a next – generation mobile point-of-care (POC) device.

CALAO Systems: It is the specialist of onboard connected computers.

eVaderis: It offers energy efficient, low power mixed – signal data – centric control processors.

Enerstone: It works with rechargeable battery manufacturers and integrators to improve the charge quality of their batteries.

Exagan: It is a leading supplier of Gallium Nitride based transistor devices.

Feeligreen: It provides micro – current devices for dermo – cosmetics and dermo – therapeutics.

Grapheat: It is a young startup specialized in the production and integration of monolayer high – quality of graphene on wafers and substrates for specific applications.

Gridbee Communications: It is developing Innovative long range Mesh Network solution for connected objects.

Heyday: It develops semiconductor ICs for the power conversion market.

Irlynx: It develops and commercializes infrared sensors.

Nessos Information Technologies SA: Nessos is a highly qualified software development company.

Nocilis Materials: It offers various silicon based semiconductor materials.

Noivion: It developed and patented a new thin film deposition technique named Ionized Jet Deposition (IJD).

PETsys Electronics SA: It developed new PET detectors for next generation of medical PET scanners.

Pollen Technology: It is a software company.

Scint-X: It develops and produces cutting – edge structured scintillators.

Silicon Line: A leading global provider of innovative ultra – low power optical link technology for mobile and consumer electronics markets.

Smoltek AB: It offers a proprietary conductive nano – scale carbon technology.

Wavelens: It is developing disruptive optical MEMS solutions.

On October 7, there will be a five-minute pitch for each start-up participating. It will be followed by a panel discussion: ‘Fundraising for the Future Champions of European Electronics: Strategies, Challenges and Opportunities. Day two will host the Innovation conference.

Categories: Semiconductors

DVCon India 2014 aims to bring Indian design, verification and ESL community closer!

September 11, 2014 5 comments

DVCon India 2014 has come to Bangalore, India, for the first time. It will be held at the Hotel Park Plaza in Bangalore, on Sept. 25-26. Dr. Wally Rhines, CEO, Mentor Graphics will open the proceedings with his inaugural keynote.

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Gaurav Jalan, SmartPlay, chair – promotions committee took time to speak about DVCon 2014 India.

Focus of DVCon 2014 India

First, what’s the focus of DVCon 2014 India? According to Jalan, DVCon has been a premiere conference in the US contributing to quality tutorials, papers and an excellent platform for networking. DVCON India focuses on filling the void of a vendor neutral quality conference in the neighbourhood – one that will grow over time.

The idea is to bring together, hitherto dispersed, yet substantial, design, verification and ESL community and give them a voice. Engineers get a chance to learn solutions to the verification problems, share the effectiveness of the solutions they have experimented, understand off the shelf solutions that are available in market and meet the vendor agnostic user fraternity. Moving forward the expectation is to get the users involved as early adopters of upcoming standards and actively contribute to them.

Trends in design

Next, what are the trends today in design? Jalan said while the designs continue to parade on the lines of Moore’s law there is a lot happening beyond the mere gate count. Defining and developing IPs with a wide configuration options serving a variety of application domains is a challenge.

The SoCs are crossing multi billion gate design (A8 in iPhone6 is 2 billion) with multi-fold increase in complexity due to multiple clock domains, multiple power domains, multiple voltage domains while delivering required performance in different application modes with sleek foot print.

Trends in verification

Now, let’s examine the trends today in verification. When design increases linearly, verification jumps exponentially. While UVM has settled dust to some extent on the IP verification level, there is a huge of challenges still awaiting to be addressed. The IP itself is growing in size limiting the simulator and encouraging users to move to emulators. While UVM solved the methodology war the VIPs available are still not simulator agnostic and expecting a emulator agnostic VIP portfolio is still a distant dream.

SoC verification is still a challenge not just due to the sheer size but because porting an env from block to SoC is difficult. The test plan definition and development for SoC level itself is a challenge. Portable stimulus group from Accellera is addressing this.

Similarly, coverage collection from different tools is difficult to merge. Unified coverage group at Accellera is addressing this. Low power today is a norm and verifying a power aware design is quite challenging. UPF is an attempt to standardize this.

Porting a SoC to emulator to enable hardware acceleration so as to run usecases is another trend picking up. Teams now are able to boot android on an SoC even before the silicon arrives. With growing analog content on chip the onus is on the verification engineers to ensure the digital and analog sides of the chip work in conjunction as per specs. Formal apps have picked so as to address connectivity tests, register spec testing, low power static checks and many more.

Accelearating EDA innovation

So, how will EDA innovation get accelerated? According to Jalan, the semiconductor industry has always witnessed that startups and smaller companies lead the innovation. Given the plethora of challenges around, there are multiple opportunities to be addressed from both the biggies and the start-ups.

The evolution of standards at Accellera definitely is a great step so as to bring the focus on real innovation in the tools while providing a platform for the user community to come forward sharing the challenges and proposing alternates. With a standard baseline that is defined with collaboration from all partners of the ecosystem, the EDA companies can focus on competing on performance, user interface, increased tool capacity and enabling faster time to market.

Forums like DVCON India help in growing awareness on standard promoted by Accellera while encouraging participants from different organizations and geographies join to contribute. Apart from tools areas where EDA innovation would pick up include new IT technologies and platforms – Cloud, Mobile devices.

Next level of verification productivity

Where is the next level of verification productivity likely to come from? To this, Jalan replied that productivity in the verification improves from different aspects.

While faster tools with increased capacity comes from innovation at EDA end, standard have played an excellent role in addressing it. UVM has helped in displacing vendor specific technologies to improve inter-operability, quick ramp up for engineers and reusability. Similarly on power format, UPF has played an important role in bridging the gaps.

Unified coverage is another aspect where it will help in closing early with coverage driven verification. IPXACT and SystemRDL standards help further in packaging IPs and easier hand off to enable reuse. Similarly other standards on ESL, AMS etc help in closing the loop holes that prevent productivity.

New, portable stimulus specification now being developed under Accellera that will help in easing out test development at different levels from IP to sub system to SoC. For faster simulations, the increase in adoption of hardware acceleration platforms is helping verification engineers to improve regression turn around time.

Formal technologies play an important role in providing a mathematical proofs to common verification challenges at an accelerated pace in comparison to simulation. Finally events like DVCON enables users to share their experiences and knowledge encouraging others to try out solutions instead of struggling with the process of discovering or inventing one.

More Indian start-ups

Finally, do the organizers expect to see more Indian start-ups post this event? Yes, says Jalan. “We even have a special incubation booth that is encouraging young startups to come forth and exhibit at a reduced cost (only $300). We are creating a platform and soon we will see new players in all areas of Semiconductor.

“Also, the Indian government’s push in the semiconductor space will give new startups further incentive to mushroom. These conferences help entrepreneurs to talk to everyone in the community about problems, vet potential solutions and seek blessings from gurus.”

Categories: Semiconductors

Apple continues to ‘wow’ all over again!

September 9, 2014 4 comments

Apple iPhone6

Apple iPhone6

Apple has done it again! Trust the Cupertino-based company to come up with great products — time after time, after time!

Today, the iPhone 6 and iPhone 6 Plus have been announced! These were followed quickly by announcements regarding the Apple Watch and Apple Pay.

The phones have 4.7-inch and 5.5-inch Retina HD displays, and packed with innovative technologies in an all-new dramatically thin and seamless design. Also, they are engineered to be the thinnest ever. Both models run on the all-new A8 chip and include iOS 8, the very latest version!

The Apple Pay now allows a very easy way to securely pay for physical goods and services in stores or apps with the touch of a finger. You can pay securely and conveniently in stores by holding the phone near the contactless reader and keeping a finger on Touch ID. There is absolutely no need to unlock your iPhone or launch an app!

The Apple Watch introduces a specially designed and engineered Digital Crown that provides an innovative way to scroll, zoom and navigate. It is Apple’s most revolutionary navigation tool since the iPod Click Wheel and iPhone Multi-Touch.

Analysys Mason believes that smartwatches will become the dominant wearable smart device by sales in early 2017, and that, Apple will drive this market. Analysys Mason also feels that Apple has an advantage in the race for mobile commerce and payments dominance.

IHS reports that Apple rarely invents new markets, despite its reputation. But when Apple launches a new product category, it attempts to redefine the market. Apple Pay may also get introduced internationally as soon as possible.

Categories: Semiconductors
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