Wow! Yesterday, Synopsys signed a definitive agreement to acquire Magma Design Automation Inc. This news is interesting, and not surprising. This acquisition seemed to be on the cards, but at least, not so soon. Nevertheless!
So, that leaves Synopsys, Cadence and Mentor Graphics as the big three EDA vendors, now that Magma has been acquired.
Just a couple of months back, I was in discussion with Rajeev Madhavan, chairman and CEO, Magma, regarding Silicon One technology solutions on the sidelines of MUSIC India. Magma had outlined five technologies: Talus, Tekton, Titan, FineSim and Excalibur and expected to have the opportunity to be a dominant yield management company.
Where has all of this gone, one wonders! It can safely be assumed that the Silicon One series can very well go on, now under the guidance of Synopsys. However, it will only add up to boosting the revenues of Synopsys in the long run.
Some time ago, one thought that the EDA industry was having four big players. Now, there are three. In between, there was news such as Cadence trying to acquire Mentor Graphics, which did not happen. Even Magma seemed to be doing fine, at least, till 2006-07.
Thereafter, it has been a slightly different story, with not only the CEO leaving Magma India, and some changes in the Indian management team, as well as certain MUSIC India events with less attendances, and so on. One can accept these as the part and parcel for any industry/organization.
On Magma’s website, there is a statement from Madhavan, which says: “Magma and Synopsys have always shared a common goal of enabling chip designers to improve performance, area and power while reducing turnaround time and costs on complex ICs,” said Rajeev Madhavan, CEO of Magma. “By joining forces now we can ensure that chip designers have access to the advanced technology they need for silicon success at 28, 20 nanometer and below.”
All the best to both Synopsys and Magma!
Presenting the excerpts from the welcome address by Debasish Paul Choudhury, president, SEMI India, at the ongoing Solarcon India 2011, being held in Hyderabad.
This year’s show features a larger exhibition, a three-day dual track conference, and will feature three concurrent technical programs. The theme for this year’s exposition, representing the widening solar value chain in India, is “Showcasing the Solar Eco‐System: From Polysilicon to Power Plants.”
The exhibition with over 115 exhibitors from eight countries, compared to 81 exhibitors in SOLARCON India 2010, covers the entire solar value chain, will provide you an opportunity to see a wide range of new products and services offered by Indian and international companies, under one roof.
This year’s show, as many of you are aware, is certified by the US Department of Commerce (US DOC), and features an exclusive US Pavilion with 14 leading US companies participating in the exhibition. I am also delighted to welcome a 35-member Clean Tech Delegation led by the USA’s Under Secretary of Commerce for International Trade, Francisco J. Sanchez to the show.
I am delighted to have in our midst two other distinguished guests – Dr. Bharat Bhargava, director – Photovoltaics, Ministry of New & Renewable Energy, Government of India, who is widely credited to be the architect of the India’s National Solar Mission. In the same vein, I am happy to welcome Jim Brown, president, Utility Systems Business Group, First Solar Inc., the world’s largest thin film module manufacturer, with us this morning.
Featuring more than 70 speakers drawn from the industry, academia and government, the conference is themed “Charting India’s Roadmap to Solar Leadership — Translating Potential into Reality.” The conference attracts high-profile participation of solar energy leaders from all segments of the industry supply chain, academia and governments from India and around the world.
The three-day conference also includes an LED Lighting summit, co-organized with Frost & Sullivan, which will focus on SSL (solid state lighting) technology with speakers from among LED manufacturers, LED suppliers, researchers and others.
The climate in which we are holding the show this year has not been without its challenges – on two fronts: the events in Hyderabad on the one hand (which have now, we are grateful to all parties involved, returned to complete normalcy) and the considerable stress that the solar industry is under due the slowdown in the European economies, regulatory changes in the major solar markets and manufacturing over capacity resulting in a fall in PV system prices over the last two to three quarters.
This show and the support it has received are proof that the long term prospects for the solar industry remain most bright in India.
Early this month, STMicroelectronics and Freescale Semiconductor introduced a new dual-core microcontroller (MCU) family aimed at functional safety applications for car electronics.
These 32-bit devices help engineers address the challenge of applying sophisticated safety concepts to comply with current and future safety standards. The dual-core MCU family also includes features that help engineers focus on application design and simplify the challenges of safety concept development and certification.
Based on the industry-leading 32-bit Power Architecture technology, the dual-core MCU family, part-numbered SPC56EL at ST and MPC564xL at Freescale, is ideal for a wide range of automotive safety applications including electric power steering for improved vehicle efficiency, active suspension for improved dynamics and ride performance, anti-lock braking systems and radar for adaptive cruise control.
The Freescale/STMicroelectronics joint development program (JDP) is headquartered in Munich, Germany, and jointly managed by ST and Freescale.
The JDP is accelerating innovation and development of products for the automotive market. The JDP is developing 32-bit Power Architecture MCUs manufactured on 90nm technology for an array of automotive applications: a) powertrain, b) body, c) chassis and safety, and d) instrument cluster.
STMicroelectronics’ SK Yue, said: “We are developing 32-bit MCUs based on 90nm Power Architecture technology. One unique feature — it allows customer to use dual core or single core operation. The objective of this MCU is to help customers simplify design and to also reduce the overall system cost.
On the JDP, he added: “We will have more products coming out over a period of time. This JDP is targeted toward automotive products.”
Commenting on the automotive market today, he said that from June onward, the industry has been witnessing a gradual sign of recovery coming in the automotive market.
Automotive market challenges
There has been an increasing integration and system complexity. These include:
* Increasing electrification of the vehicle (replacing traditional mechanical systems).
* Mounting costs pressure leading to integration of more functionality in a single ECU.
* Subsequent increase in use of high-performance sensor systems has driven increased MCU performance needs.
There are also increasing safety expectations. Automotive system manufacturers need to guarantee the IEC61508 (SIL3) and ISO26262 (ASILD) system-safety capability. Also, a move from passive to active safety is increasing the number of safety functions distributed in many ECUs.
Finally, there is a continued demand for quality — in form of zero defects, by which, a 10x quality improvement is expected.
MCU family addresses market challenges
The MCU family offers exceptional integration and performance. These include: high-end 32-bit dual-issue Power Architecture cores, combined with comprehensive peripheral set in 90nm non-volatile-memory technology. It also provides a cost effective solution by reducing board size, chip count and logistics/support costs.
It also solves functional safety. The Functional Safety architecture has been specifically designed to support IEC61508 (SIL3) and ISO26262 (ASILD) safety standards. The architecture provides redundancy checking of all computational elements to help endure the operation of safety related tasks. The unique, dual mode of operation allows customers to choose how best to address their safety requirements without compromising on performance.
The MCU also offers best-in-class quality. It is design for quality, aiming for zero defects. The test and manufacture have been aligned to lifetime warranty needs.
The MCU family addresses the challenges of applying sophisticated safety concepts to meet future safety standards. Yue added, “There are two safety standards — we are following those guidelines.” These are the IEC61508 (SIL3) and ISO26262 (ASILD) system-safety capabilities.
The automotive industry is also targeting for zero defects. “Therefore, all suppliers in tier 1 and 2 need to come up with stringent manuyfaturing and testing process that ensures zero defects,” he said.
32-bit dual-issue, dual-core MCU family
Finally, why dual core? Yue said that the MCU helps customers to achieve to achieve safety and motor control. Hence, dual core will definitely help deliver results.
“In many automotive applications, especially in safety-related applications, we want to have redundancy for safety. In the lock-step mode, two cores run the same task simultaneously, and results are then compared to each other in every computation. If the results are not matched, it indicates that there are some problems.”
This MCU family definitely simplifies design. It uses a flexible, configurable architecture that addresses both lock-step and dual parallel operation modes on a single dual-core chip. Next, it complies with safety standards.
A redundant architecture provides a compelling solution for real-time applications that require compliance with the IEC61508 SIL3 and ISO26262 ASIL-D safety standards. It also lowers the systems cost.
Dual-core architecture reduces the need for component duplication at the system level, and lowers overall system costs.
Recently, MindTree launched its Intelligent Video Surveillance System (IVSS). Though it seems to be a bit late in the market, the solution has tremendous potential.
Video surveillance globally is said to be a $13 billion market. In India, there has been a huge budget allocation for security worth Rs. 33,000 crores. According to MindTree, its focus is on intelligence, and that would be the company’s differentiator in the years to come.
Technology drivers for such devices include — a move from analog to IP; from networked to distributed; intelligence and analysis; use of allied technologies and standardization.
According to MindTree’s Sharmila Saha, the company wants to become an end-to-end solution provider. Its main value proposition is to bring management and analytics into all of its solutions. MindTree also has a enterprise ready hybrid product that supports both analog and IP cameras. It is starting ready to manufacture/IP licensing products.
Commenting on typical IVSS market and its characteristics, she said these included:
* public infrastructure, defence, educational institutions, etc.,
* financial institutions, retail, enterprise and home,
* server-based storage (networked video recording), and
* server based analytics.
MindTree’s differentiators are said to be the following: video analytics — the solution allows searching metadata, bandwidth management, security managenent — including tamper detection, video watermarking and secure transmission of data; and deployment — MindTree is also going standard compliant, supports multi-vendor devices, and offers customizable solutions.
Let us take a look at some of the features of MindTree’s solutions. Users can certainly do PTZ remotely, and also set camera in the patrol mode. Digital zoom is yet another feature. Image detection is done at 30fps. Image stiching is yet another feature available.
Searches can be done based on both time and data. There is also an events browser. Schedule recording can be performed by setting certain rules. H.264 is used for compressing images. MindTree has also built in face detection and face recognition as part of its video algorithms, besides Virtual TripWire.
S. Janakiraman, President and Group CEO, Product Engineering Services, pointed out that several other algorithms are being developed at the Indian Institute of Science, Bangalore. Another algorithm — image stitching — has been developed by MindTree.
The company is filing the patent for image stitching, as well as for face detection. MindTree can control the storage and network costs since its own algorithms are being used. According to him, the company is in talks with the defence, etc.
MindTree’s network surveillance system helps an existing analog surveillance system to migrate to a centralized and IP based video surveillance system while still exploiting the investment on the analog infrastructure.
Built modularly, the IVSS comprises of multiple components that can also be used individually to increase operational efficiency. OEMs can leverage the reference design from MindTree for creating their own hybrid DVRs and system integrators can use the ready-to-fit solution accelerators and components to provide more robust and flexible surveillance systems to end customers.
IVSS key components
* Digital Video Recorder (DVR)
* Network Video Recorder (NVR)
* Video Management Solution (VMS)
* Video Analytics Algorithms Suite (VAAS)
* Analog-to-IP Encoders
* Smart IP Cameras
Key features of IVSS system:
* Video analytics with distributed intelligence to trigger specific actions on alerts and alarms.
* Intelligent video mining to extract valuable information from raw feed quickly and efficiently.
* Bandwidth management to reduce IP bandwidth requirements for feed transmission.
* Single management station that is scalable for future requirements.
* Reliable alarm management that is configurable for any event.
* Multi-camera tracking for specific objects through multiple cameras.
* Enhanced security features including watermarking and tamper protection.
BANGALORE, INDIA: Texas Instruments Inc. (TI) recently introduced a dual, 14-bit analog-to-digital converter (ADC), the ADS62P49, at 250MSPS to deliver a premier combination of wide signal bandwidth, high dynamic performance and low power consumption.
The ADS62P49 achieves 73-dBFS signal-to-noise (S/N) ratio and 85-dBc spurious-free dynamic range (SFDR) at an input frequency of 60 MHz. I was able to catch up with Apoorva Awasthy, Business Development Manager, High Performance Analog, Texas Instruments India, to find out more about this new 14-bit ADC.
Chief features of TI 14-bit ADC
Texas Instruments (TI) has united speed and efficiency with the industry’s fastest dual, 14-bit ADC at 250 MSPS. Key features of this device include:
* It delivers a premier combination of wide signal bandwidth, high dynamic performance and low power consumption;
* Fastest dual, 14-bit ADC at 250MSPS enables multi-channel, wide-bandwidth sampling without sacrificing dynamic performance, for enhanced accuracy in portable test equipment;
* Low power of 625 mW per channel reduces thermal footprint for increased system efficiency in high-density, multi-antenna base station receivers and software defined radios;
* Programmable gain and other user-selectable settings maximizes design flexibility;
* Complete signal chain with comprehensive evaluation tools suite speeds time to market; and
* It is first in a series of four 12- and 14-bit dual channel ADCs with sample rates of 210MSPS and 250MSPS, respectively.
TI also says that the 250-MSPS data converter provides 66 percent greater bandwidth than competing dual ADCs. Has this been based on any on-field performance? Awasthy said that this is the performance specified in the data sheet and was tested in a lab.
Naturally, the key application areas would be interesting to look at! Awasthy said, “The ADS62P49 is suitable for applications such as communications and defense imaging systems, and wide-band test and measurement equipment. The block diagram given here shows an application area.Source: TI
Again, when TI says that the ADS62P49 has the “the industry’s fastest sample rate”, what’s the benchmark? Awasthy said, “We have done comparisons between our device and others in the industry. We are the only one to offer a dual, 14-bit device that achieves 250MSPS.”
Solving customer challenges
What are the main customer challenges solved by the new ADC? Awasthy said: “Communications, defense and test design engineers are constantly challenged to create signal and data acquisition receivers with increasingly wide signal bandwidths that do not compromise overall system performance. Another key feature in demand is the low power capabilities without bargaining on performance.
“TI addresses these challenges with the ADS62P49, which delivers high-performance, compact, power-efficient designs, and enables rapid deployment of 3G and 4G systems, software defined radios and spectrum analyzers.”
What if the competition brings out such a device or a better one soon? TI is not in a position to speculate on what the competition is planning. “The data converter market offers tremendous opportunities to TI. We will continue to offer leading edge data converters that address our customers’ challenges and advance next generation system design,” he added.
This is the first in a series of four 12- and 14-bit dual channel ADCs. Awasthy said that TI expects more of such devices to be released in the second half of this year.
EDA is a complex industry to be in, what with process geometries changing all the time and EDA firms compelled to keep up with those changes. Magma Design Automation Inc. has been one of those, which has kept ahead of the changes and also managed good growth. In other words, Magma has managed to beat the clock consistently and stayed ahead, and continues to do so.
According to Rajeev Madhavan, chairman and CEO, Magma Design Automation Inc.. Magma has been outperforming the EDA industry by 2x globally. He touched upon the drive toward consumerization. Whle it was driven by PCs during the 1980s, mobile phones and PDAs are now the growth drivers for the common man. The consumer space is driving semiconductor applications as well. These are in form of devices with smaller form factors, where power is an important issue.
As an example, Madhavan highlighted the fact that 75 percent of the chips in the iPhone type of complex cell phone has been done using Magma. “We enable such points to happen. Consumer applications are driving EDA, and we are providing that change.”
According to him, India is a major center for Magma. An entire business line of products are now being driven out of India. The physical verification units – DRC, etc., — are all done here. Magma is consistently developing new products and product lines. Any MNC in India has an opportunity to build relationships with the EDA powerhouse.
EDA is all about integration. With operating margins getting slimmer, most companies have been moving to Fab-Lite. India has great expertise in design knowledge. India should shift its focus on developing the intellectual knowledge side, contended Madhavan. As for fabs, as and when those happen in India, they will definitely create jobs. “Fab-lite is actually good for EDA. It means more design productivity. Leading firms such as TI, NVIDIA, Broadcom, etc., are our customers,” he said.
Magma is now looking at more value addition and faster development. It has covered the entire EDA domain. Magma has a culture of rewriting its software a lot more and also covers all new process geometries. According to Madhavan, Magma is constantly in touch with leading foundries such as TSMC.
It is said that right now, around 75 percent of the chips in 45nm currently use Magma. Magma is also working with a customer in 32nm. Madhavan said: “You have to develop the tools as the processes change. At Magma, we need smart people who can understand electrical engineering and computer science. Growth comes in identifying and building the talent pools.”
As for product lines developed in India, Magma’s Quartz Formal has been developed largely in India. Most of the development work is happening in NOIDA, near Delhi. Work on DRC is being done out of Bangalore. “Every single product from Magma has some footprint in India,” he said. The complexities of chips have been growing and those require more automation.
Magma intends to grow from $178 million to $211 million during 2008. Madhavan felt that as the eco-system units come up in India, the company can move forward. Magma is hopeful that more design companies will be getting into India.
90nm designs major in India
Ricky Bedi, Senior Director, Application Engineering, Magma Design Automation India Pvt Ltd, added that the EDA industry had moved on from being optimizers. India too has to now move forward from being outsourcers to enablers.
He said, “When that happens, India will play a bigger role and offer more services. For example, Wipro, etc., are now doing full turnkey solutions.” Magma India is now working with over 32 universities, regional engineering colleges (RECs), IITs, etc. The intent is to facilitate VLSI programs in all of those places.
However, he agreed that the innovation has not really kicked off in the country. As of now, 90nm designs are in the majority in India, and in comparison, 65nm designs are lesser. Magma has already gone into 45nm, and even into 32nm. Bedi said: “Right now, yield is imperative in 45nm. Innovation will continue in the smaller geometries. Innovation has to focus more on predictability, etc.”
There is another trend worth mentioning — about re-usable IPs. According to Magma, there will be even more of re-usable IPs. As the designs themselves get complex, designers need to achieve those in shorter timeframes as the time-to-market (TTM) is crucial. Replication of blocks is also happening. Implementation of re-usable IPs will go up a notch, added Bedi.
While the EDA tools are now catching up with the advances in semiconductors, it has not been smooth sailing for language. Bedi added: “As far as language is concerned, language itself does not blend so easily. It takes great effort to move from Verilog to VHDL.”
Yatin Trivedi, director, Industry Partnership Program, Design Implementation Business Unit, Magma Design Automation Inc., touched upon the aspect of power. He said: “In the EDA format, it is important that the power format is accepted by as many vendors. The difference should be in the usage, not the format. In any design flow — from RTL to GDS — any design that is implemented must be simulated. Power information is now an integral part of the design. Leakage can destroy a die.”
SEMICON Europa 2014 will be held at Grenoble, France, on October 7-9 October, 2014. The event will see over 400 exhibitors, which means, the exhibition area has expanded by over 40 percent vs. 2013. There will be over 70 programs featuring 300+ speakers. SEMI expects 6,000+ visitors.
A feature of the event will be the Innovation Village that will feature 35 start-ups. I have been just informed that four start-ups have cancelled. So, that leaves 31 start-ups: ActLight, Aryballe, Avalun, Bluwireless Technology, CALAO Systems, Enerstone, Euresis, Epigan, Evaderis, Exagan, Feeligreen, Genes’Ink, Grapheat, Gridbee, Heyday, Hotblock Onboard, Imagsa Technology, Irlynx, Madci, Metablue Solution, Nessos, Nocilis Materials, Noivion, PETsys Electronics, Pollen Technology, Scint-X, Sepcell, Silicon Line GmbH, Smoltek, Sol Voltaics and Wavelens.
A few start-ups are given below:
ActLight SA: It focuses in the field of CMOS photonics.
AVALUN SAS: It currently develops the LabPad®, a next – generation mobile point-of-care (POC) device.
CALAO Systems: It is the specialist of onboard connected computers.
eVaderis: It offers energy efficient, low power mixed – signal data – centric control processors.
Enerstone: It works with rechargeable battery manufacturers and integrators to improve the charge quality of their batteries.
Exagan: It is a leading supplier of Gallium Nitride based transistor devices.
Feeligreen: It provides micro – current devices for dermo – cosmetics and dermo – therapeutics.
Grapheat: It is a young startup specialized in the production and integration of monolayer high – quality of graphene on wafers and substrates for specific applications.
Gridbee Communications: It is developing Innovative long range Mesh Network solution for connected objects.
Heyday: It develops semiconductor ICs for the power conversion market.
Irlynx: It develops and commercializes infrared sensors.
Nessos Information Technologies SA: Nessos is a highly qualified software development company.
Nocilis Materials: It offers various silicon based semiconductor materials.
Noivion: It developed and patented a new thin film deposition technique named Ionized Jet Deposition (IJD).
PETsys Electronics SA: It developed new PET detectors for next generation of medical PET scanners.
Pollen Technology: It is a software company.
Scint-X: It develops and produces cutting – edge structured scintillators.
Silicon Line: A leading global provider of innovative ultra – low power optical link technology for mobile and consumer electronics markets.
Smoltek AB: It offers a proprietary conductive nano – scale carbon technology.
Wavelens: It is developing disruptive optical MEMS solutions.
On October 7, there will be a five-minute pitch for each start-up participating. It will be followed by a panel discussion: ‘Fundraising for the Future Champions of European Electronics: Strategies, Challenges and Opportunities. Day two will host the Innovation conference.
DVCon India 2014 has come to Bangalore, India, for the first time. It will be held at the Hotel Park Plaza in Bangalore, on Sept. 25-26. Dr. Wally Rhines, CEO, Mentor Graphics will open the proceedings with his inaugural keynote.
Gaurav Jalan, SmartPlay, chair – promotions committee took time to speak about DVCon 2014 India.
Focus of DVCon 2014 India
First, what’s the focus of DVCon 2014 India? According to Jalan, DVCon has been a premiere conference in the US contributing to quality tutorials, papers and an excellent platform for networking. DVCON India focuses on filling the void of a vendor neutral quality conference in the neighbourhood – one that will grow over time.
The idea is to bring together, hitherto dispersed, yet substantial, design, verification and ESL community and give them a voice. Engineers get a chance to learn solutions to the verification problems, share the effectiveness of the solutions they have experimented, understand off the shelf solutions that are available in market and meet the vendor agnostic user fraternity. Moving forward the expectation is to get the users involved as early adopters of upcoming standards and actively contribute to them.
Trends in design
Next, what are the trends today in design? Jalan said while the designs continue to parade on the lines of Moore’s law there is a lot happening beyond the mere gate count. Defining and developing IPs with a wide configuration options serving a variety of application domains is a challenge.
The SoCs are crossing multi billion gate design (A8 in iPhone6 is 2 billion) with multi-fold increase in complexity due to multiple clock domains, multiple power domains, multiple voltage domains while delivering required performance in different application modes with sleek foot print.
Trends in verification
Now, let’s examine the trends today in verification. When design increases linearly, verification jumps exponentially. While UVM has settled dust to some extent on the IP verification level, there is a huge of challenges still awaiting to be addressed. The IP itself is growing in size limiting the simulator and encouraging users to move to emulators. While UVM solved the methodology war the VIPs available are still not simulator agnostic and expecting a emulator agnostic VIP portfolio is still a distant dream.
SoC verification is still a challenge not just due to the sheer size but because porting an env from block to SoC is difficult. The test plan definition and development for SoC level itself is a challenge. Portable stimulus group from Accellera is addressing this.
Similarly, coverage collection from different tools is difficult to merge. Unified coverage group at Accellera is addressing this. Low power today is a norm and verifying a power aware design is quite challenging. UPF is an attempt to standardize this.
Porting a SoC to emulator to enable hardware acceleration so as to run usecases is another trend picking up. Teams now are able to boot android on an SoC even before the silicon arrives. With growing analog content on chip the onus is on the verification engineers to ensure the digital and analog sides of the chip work in conjunction as per specs. Formal apps have picked so as to address connectivity tests, register spec testing, low power static checks and many more.
Accelearating EDA innovation
So, how will EDA innovation get accelerated? According to Jalan, the semiconductor industry has always witnessed that startups and smaller companies lead the innovation. Given the plethora of challenges around, there are multiple opportunities to be addressed from both the biggies and the start-ups.
The evolution of standards at Accellera definitely is a great step so as to bring the focus on real innovation in the tools while providing a platform for the user community to come forward sharing the challenges and proposing alternates. With a standard baseline that is defined with collaboration from all partners of the ecosystem, the EDA companies can focus on competing on performance, user interface, increased tool capacity and enabling faster time to market.
Forums like DVCON India help in growing awareness on standard promoted by Accellera while encouraging participants from different organizations and geographies join to contribute. Apart from tools areas where EDA innovation would pick up include new IT technologies and platforms – Cloud, Mobile devices.
Next level of verification productivity
Where is the next level of verification productivity likely to come from? To this, Jalan replied that productivity in the verification improves from different aspects.
While faster tools with increased capacity comes from innovation at EDA end, standard have played an excellent role in addressing it. UVM has helped in displacing vendor specific technologies to improve inter-operability, quick ramp up for engineers and reusability. Similarly on power format, UPF has played an important role in bridging the gaps.
Unified coverage is another aspect where it will help in closing early with coverage driven verification. IPXACT and SystemRDL standards help further in packaging IPs and easier hand off to enable reuse. Similarly other standards on ESL, AMS etc help in closing the loop holes that prevent productivity.
New, portable stimulus specification now being developed under Accellera that will help in easing out test development at different levels from IP to sub system to SoC. For faster simulations, the increase in adoption of hardware acceleration platforms is helping verification engineers to improve regression turn around time.
Formal technologies play an important role in providing a mathematical proofs to common verification challenges at an accelerated pace in comparison to simulation. Finally events like DVCON enables users to share their experiences and knowledge encouraging others to try out solutions instead of struggling with the process of discovering or inventing one.
More Indian start-ups
Finally, do the organizers expect to see more Indian start-ups post this event? Yes, says Jalan. “We even have a special incubation booth that is encouraging young startups to come forth and exhibit at a reduced cost (only $300). We are creating a platform and soon we will see new players in all areas of Semiconductor.
“Also, the Indian government’s push in the semiconductor space will give new startups further incentive to mushroom. These conferences help entrepreneurs to talk to everyone in the community about problems, vet potential solutions and seek blessings from gurus.”
The EDA 360 was an industry vision. It reflected a change in market requirements. It was application driven system design. From a Cadence perspective, the company has done system design enablement, according to Nimish Modi, senior VP, marketing and business development, Cadence Design Systems Inc.
In Apple’s case, the iOS is unique. Cadence feels that the heart of the design is the SoC. The electrical analysis is becoming very important. For instance, how do you optimize before tape-out? Hardware and software conversion presents a huge problem as well. The IP plays an important part. Cadence did IP-as-a-service. It now has an IP strategy.
Today, EDA is about possibility, not productivity. Cadence provides tools and content for semiconductor and systems companies. It is now realizing the EDA 360 vision.
According to Modi, each IP is immensely complex. Standards based or interface IP is not enough! Silicon-proven design is the need of the hour. Now, more and more IP blocks are said to be coming together.
Cadence is offering the Palladium XP, and its primary use is for system verification. Software development is becoming a little bit difficult. People are providing software prototypes. The Palladium compile, turnaround and debug are very fast, best-in-class. All memory, clocking, partitioning, etc., is now automated.
The capacity of the Protium platform is 100 million gates. It will enable hardware and software developers. The use model for Protium is:
* Hardware folks use it for hardware regression.
* Software folks use it for early software development.
The main value proposition is the faster bring-up time. Also, the Palladium hybrid model helps customers overcome the boot problem. It is a hybrid of emulation and virtual prototyping. The dynamic power analysis is another issue. The Palladium hybrid model helps to do the testing.
Collaboration with ARM
ARM provides processor IPs. Cadence works closely with ARM. Cadence is also co-optimizing its tools to provide the best PPA. Physical libraries and tools get optimized. Cadence’s tools are optimized for ARM architecture. Cadence is also the first ones on the access to the V8 ARM models.