According to Dr. Walden C. Rhines, chairman and CEO, Mentor Graphics Corp., verification has to improve and change every year just to keep up with the rapidly changing semiconductor technology. Fortunately, the innovations are running ahead of the technology and there are no fundamental reasons why we cannot adequately verify the most complex chips and systems of the future. He was speaking at the recently held DVCON 2014 in Bangalore, India.
A design engineer’s project time for doing design has reduced by 15 percent from 2007-2014, while the engineer’s time for doing verification had seen 17 percent increase during the same time. At this rate, in about 40 years, all of a designer’s time will be devoted to verification. At the current rate, there is almost no chance of getting a single-gate design correct on first pass!
Looking at a crossover of verification engineers vs. designer engineers, there is a CAGR designers of 4.55 percent, and for CAGR verifiers, it is 12.62 percent.
The on-time completion remains constant, as we look at the non-FPGA project’s schedule completion trends, which are: 67 percent behind schedule for 2007, 66 percent behind schedule for 2010, 67 percent behind schedule for 2012, and 59 percent behind schedule for 2014. There has been an increase in the average number of embedded processors per design size, moving from 1.12 to 4.05.
Looking at the macro trends, there has been standardization of verification languages. SystemVerilog is the only verification language growing. Now, interestingly, India leads the world in SystemVerilog adoption. It is also remarkable that the industry converged on IEEE 1800. SystemVerilog is now mainstream.
There has been standardization in base class libraries as well. There was 56 percent UVM growth between 2012 and 2014, and 13 percent is projected growth in UVM the next year. Again, India leads the world in UVM adoption.
The second macro trend is standardization of the SoC verification flow. It is emerging from ad hoc approaches to systematic processes. The verification paradox is: a good verification process lets you get the most out of best-in-class verification tools.
The goal of unit-level checking is to verify that the functionality is correct for each IP, while achieving high coverage. Use of advanced verification techniques has also increased from 2007 to 2014.
Next, the goal of connectivity checking is to ensure that the IP blocks are connected correctly, a common goal with IP integration and data path checking.
The goal of system-level checking is performance, power analysis and SoC functionality. Also, there are SoC ‘features’ that need to be verified.
A third macro trend is the coverage and power across all aspects of verification. The Unified Coverage Interoperability Standard or UCIS standard was announced at DAC 2012 by Accellera. Standards accelerate the EDA innovation!
The fourth trend is active power management. Now, low-power design requires multiple verification approaches. Trends in power management verification include things like Hypervisor/OS control of power management, application-level power management, operation in each system power state, interactions between power domains, hardware power control sequence generation, transitions between system power states, power domain state reset/restoration, and power domain power down/power up.
Macro enablers in verification
Looking at the macro enablers in verification, there is the intelligent test bench, multi-engine verification platforms, and application-specific formal. The intelligent test bench technology accelerates coverage closure. It has also seen the emergence of intelligent software driven verification.
Embedded software headcount surges with every node. Clock speed scaling slows the simulation performance improvement. Growing at over 30 percent CAGR from 2010-14, emulation is the fastest growing segment of EDA.
As for system-level checking, as the design sizes increase emulation up, the FPGA prototyping goes down. The modern emulation performance nmakes virtual debug fast. Virtual stimulus makes emulator a server, and moves the emulator from the lab to the datacenter, thereby delivering more productivity, flexibility, and reliability. Effective 100MHz embedded software debug makes virtual prototype behave like real silicon. Now, integrated simulation/emulation/software verification environments have emerged.
Lastly, for application-specific formal, the larger designs use more formal. The application-specific formal includes checking clock domain crossings.
DVCon India 2014 has come to Bangalore, India, for the first time. It will be held at the Hotel Park Plaza in Bangalore, on Sept. 25-26. Dr. Wally Rhines, CEO, Mentor Graphics will open the proceedings with his inaugural keynote.
Gaurav Jalan, SmartPlay, chair – promotions committee took time to speak about DVCon 2014 India.
Focus of DVCon 2014 India
First, what’s the focus of DVCon 2014 India? According to Jalan, DVCon has been a premiere conference in the US contributing to quality tutorials, papers and an excellent platform for networking. DVCON India focuses on filling the void of a vendor neutral quality conference in the neighbourhood – one that will grow over time.
The idea is to bring together, hitherto dispersed, yet substantial, design, verification and ESL community and give them a voice. Engineers get a chance to learn solutions to the verification problems, share the effectiveness of the solutions they have experimented, understand off the shelf solutions that are available in market and meet the vendor agnostic user fraternity. Moving forward the expectation is to get the users involved as early adopters of upcoming standards and actively contribute to them.
Trends in design
Next, what are the trends today in design? Jalan said while the designs continue to parade on the lines of Moore’s law there is a lot happening beyond the mere gate count. Defining and developing IPs with a wide configuration options serving a variety of application domains is a challenge.
The SoCs are crossing multi billion gate design (A8 in iPhone6 is 2 billion) with multi-fold increase in complexity due to multiple clock domains, multiple power domains, multiple voltage domains while delivering required performance in different application modes with sleek foot print.
Trends in verification
Now, let’s examine the trends today in verification. When design increases linearly, verification jumps exponentially. While UVM has settled dust to some extent on the IP verification level, there is a huge of challenges still awaiting to be addressed. The IP itself is growing in size limiting the simulator and encouraging users to move to emulators. While UVM solved the methodology war the VIPs available are still not simulator agnostic and expecting a emulator agnostic VIP portfolio is still a distant dream.
SoC verification is still a challenge not just due to the sheer size but because porting an env from block to SoC is difficult. The test plan definition and development for SoC level itself is a challenge. Portable stimulus group from Accellera is addressing this.
Similarly, coverage collection from different tools is difficult to merge. Unified coverage group at Accellera is addressing this. Low power today is a norm and verifying a power aware design is quite challenging. UPF is an attempt to standardize this.
Porting a SoC to emulator to enable hardware acceleration so as to run usecases is another trend picking up. Teams now are able to boot android on an SoC even before the silicon arrives. With growing analog content on chip the onus is on the verification engineers to ensure the digital and analog sides of the chip work in conjunction as per specs. Formal apps have picked so as to address connectivity tests, register spec testing, low power static checks and many more.
Accelearating EDA innovation
So, how will EDA innovation get accelerated? According to Jalan, the semiconductor industry has always witnessed that startups and smaller companies lead the innovation. Given the plethora of challenges around, there are multiple opportunities to be addressed from both the biggies and the start-ups.
The evolution of standards at Accellera definitely is a great step so as to bring the focus on real innovation in the tools while providing a platform for the user community to come forward sharing the challenges and proposing alternates. With a standard baseline that is defined with collaboration from all partners of the ecosystem, the EDA companies can focus on competing on performance, user interface, increased tool capacity and enabling faster time to market.
Forums like DVCON India help in growing awareness on standard promoted by Accellera while encouraging participants from different organizations and geographies join to contribute. Apart from tools areas where EDA innovation would pick up include new IT technologies and platforms – Cloud, Mobile devices.
Next level of verification productivity
Where is the next level of verification productivity likely to come from? To this, Jalan replied that productivity in the verification improves from different aspects.
While faster tools with increased capacity comes from innovation at EDA end, standard have played an excellent role in addressing it. UVM has helped in displacing vendor specific technologies to improve inter-operability, quick ramp up for engineers and reusability. Similarly on power format, UPF has played an important role in bridging the gaps.
Unified coverage is another aspect where it will help in closing early with coverage driven verification. IPXACT and SystemRDL standards help further in packaging IPs and easier hand off to enable reuse. Similarly other standards on ESL, AMS etc help in closing the loop holes that prevent productivity.
New, portable stimulus specification now being developed under Accellera that will help in easing out test development at different levels from IP to sub system to SoC. For faster simulations, the increase in adoption of hardware acceleration platforms is helping verification engineers to improve regression turn around time.
Formal technologies play an important role in providing a mathematical proofs to common verification challenges at an accelerated pace in comparison to simulation. Finally events like DVCON enables users to share their experiences and knowledge encouraging others to try out solutions instead of struggling with the process of discovering or inventing one.
More Indian start-ups
Finally, do the organizers expect to see more Indian start-ups post this event? Yes, says Jalan. “We even have a special incubation booth that is encouraging young startups to come forth and exhibit at a reduced cost (only $300). We are creating a platform and soon we will see new players in all areas of Semiconductor.
“Also, the Indian government’s push in the semiconductor space will give new startups further incentive to mushroom. These conferences help entrepreneurs to talk to everyone in the community about problems, vet potential solutions and seek blessings from gurus.”
Engineers designing FPGA applications face many challenges. Using Plunify’s automation and analysis platform, engineers can run 100 times more builds, analyze a larger set of builds and quickly zoom in on better quality results. Using data analytics and the cloud, Plunify created new capabilities for FPGA design, with InTime being an example.
Kirvy Teo said: What happens when you need to close timing in FPGA design and still can’t get it to work? Here is a new way to solve that problem – machine learning and analytics. InTime is an expert software that helps FPGA design engineers meet timing and area goals by recommending “strategies”. Strategies are combination of settings found in the existing FPGA software. With more than 70 settings available in the FPGA software, no sane FPGA design engineer have the time or capacity to understand how these affect the design outcomes.
One of the common methods now is to try random bruteforce using seeds. This is a one-way street. If you get to your desired result, great! If not, you would have wasted a bunch of time running builds with you none the wiser. Another aspect of running seeds is that the variance of the results is usually not very big, meaning you can’t run seeds on a design with bad timing scores.
However, using InTime, all builds become part of the data that we used to recommend strategies that can give you better results, using machine learning and predictive analytics. This means you will definitely get a better answer at the end of the day, and we have seen 40 percent performance improvements on designs!
How has Plunify been doing this year so far? According to Teo, Plunify did a controlled release to selected customers in first quarter of 2014, who are mainly based in China. It is easier to guess who as we nicknamed them “BCC” – Big Chinese Corporations.
Unsurprisingly, they have different methodologies to solving timing problems and design guidelines, many of which were done to pre-empt timing problems at the later stage of the design. InTime was a great way to help them to achieve their performance targets without disrupting their tool flows.
Plunify is announcing the launch of InTime during DAC and will be looking to partner with sale organizations in US.
What’s the future path likely to be? Teo added: “Machine learning and predictive analytics are one of the hottest topics and we have yet seen it being used much in chip design. We see a lot of potential in this sector. Beyond what InTime is doing now, there are still many chip design problems that can be solved with similar techniques.
“First, there is a need to determine the type of problems that can be solved with these techniques. Second, we are re-looking at existing design problems and wondering, if I can throw 100 or 1000 machines to this problem, can I get a better result? Third, how to get that better result without even running it!
“As you know, we do offer a FPGA cloud platform on Amazon. One of the most surprising observations is that people do not know how to use all those cheap power in the cloud! FPGA design is still confined to a single machine for daily work, like email. Even if I give you 100 machines, you don’t know how to check your emails faster! We see the same thing, the only method they know is to run seeds. InTime is what they need to make use of all these resources intelligently.
Why would FPGA providers take up the solution?
The InTime software works as a desktop software which can be installed in internal data centers or desktops. It is on longer just a cloud play. It works with the current in-house FPGA software that the customer already own. We are helping FPGA providers like Xilinx or Altera, by helping their customers with the designs. They will feel: How about “Getting better results without touching your RTL code!”
Agnisys Inc. was established in 2007 in Massachusetts, USA, with a mission to deliver innovative automation to the semiconductor industry. The company offers affordable VLSI design and verification tools for SoCs, FPGAs and IPs that makes the design verification process extremely efficient.
Agnisys’ IDesignSpec is an award winning engineering tool that allows an IP, chip or system designer to create the register map specification once and automatically generate all possible views from it. Various outputs are possible, such as UVM, OVM, RALF, SystemRDL, IP-XACT etc. User defined outputs can be created using Tcl or XSLT scripts. IDesignSpec’s patented technology improves engineer’s productivity and design quality.
The IDesignSpec automates the creation of registers and sequences guaranteeing higher quality and consistent results across hardware and software teams. As your ASIC or FPGA design specification changes, IDesignSpec automatically adjusts your design and verification code, keeping the critical integration milestones of your design engineering projects synchronized.
Register verification and sequences consume up to 40 percent of project time or more when errors are the source of re-spins of SoC silicon or an increase in the number of FPGA builds. IDesignSpec family of products is available in various flavors such as IDSWord, IDSExcel, IDSOO and IDSBatch.
IDesignSpec more than a tool for creating register models!
Anupam Bakshi, founder, CEO and chairman, Agnisys, said: “IDesignSpec is more than a tool for creating register models. It is now a complete Executable Design Specification tool. The underlying theme is always to capture the specification in an executable form and generate as much code in the output as possible.”
The latest additions in the IDesignSpec are Constraints, Coverage, Interrupts, Sequences, Assertions, Multiple Bus Domains, Special Registers and Parameterization of outputs.
“IDesignSpec offers a simple and intuitive way to specify constraints. These constraints, specified by the user, are used to capture the design intent. This design intent is transformed into code for design, verification and software. Functional Coverage models can be automatically generated from the spec so that once again the intent is captured and converted into appropriate coverage models,” added Bakshi.
Using an add-on function of capturing Sequences, the user is now able to capture various programming sequences in the spec, which are translated into C++ and UVM sequences, respectively. Further, the interrupt registers can now be identified by the user and appropriate RTL can be generated from the spec. Both edge sensitive and level interrupts can be handled and interrupts from various blocks can be stacked.
Assertions can be automatically generated from the high level constraint specification. These assertions can be created with the RTL or in the external files such that they can be optionally bound to the RTL. Unit level assertions are good for SoC level verification and debug, and help the user in identifying issues deep down in the simulation hierarchy.
The user can now identify one or more bus domains associated with Registers and Blocks, and generate appropriate code from it. Special Registers such as shadow registers and register aliasing is also automatically generated.
Finally all of the outputs such as RTL, UVM, etc., can be parameterized now, so that a single master specification can be used to create outputs that can be parameterized at the elaboration time.
How is IDesignSpec working as chip-level assertion-based verification?
Bakshi said: “It really isn’t an assertion tool! The only assertion that we automatically generate is from the constraints that the user specifies. The user does not need to specify the assertions. We transform the constraints into assertions.”
Selection of the right on-chip network is critical to meeting the requirements of today’s advanced SoCs. There is easy IP integration with IP cores from many sources with different protocols, and an UVM verification environment.
John Bainbridge, staff technologist, CTO Office, Sonics Inc., said that it optimizes the system performance. Virtual channels offer efficient resource usage – saves gates and wires. The non-blocking network leads to an improved system performance. There are flexible topology choices with optimal network to match requirements.
Power management is key with advanced system partitioning, and an improved design flow and timing closure. Finally, the development environment allows easy design capture and has performance analysis tools.
For the record, there are several SoC integration challenges that need to be addressed, such as IP integration, frequency, throughput, physical design, power management, security, time-to-market and development costs.
SGN exceeds requirements
SGN met the tablet performance requirement with fabric frequency of 1066MHz. It has an efficient gate count of 508K gates. There are features such as an advanced system partitioning, security and I/O coherency. There is support for system concurrency as well as advanced power management.
Sonics offers system IP solutions such as SGN, a router based NoC solution, with flexible partitioning and VC (Virtual Channel) support. The frequency is optimized with credit based flow control.
SSX/SLX is message based crossbar/ShareLink solutions based on interleaved multi-channel technology. It has target based QoS with three arbitration levels. The SonicsExpress is for power centric clock domain crossing. There is sub-system re-use and decoupling. The MemMax manages and optimizes the DRAM efficiency while maintaining system QoS. There is run-time programmability for all traffic types. The SonicsConnect is a non-blocking peripheral interconnect.
Today, EDA requires specialization. Elaborating on EDA over the past decade, Dr. Walden (Wally) C. Rhines, chairman and CEO, of Mentor Graphics, and vice chairman of the EDA Consortium, USA, said that PCB design has been flat despite growth in analysis, DFM and new emerging markets. Front end design has seen growth from RF/analog design and simulation, and analysis As design methodologies mature, EDA expenditures stop growing. He was speaking at Mentor Graphics’ U2U (User2User) conference in Bangalore, India.
Most of the EDA revenue growth comes from major new design methodologies, such as ESL, DFM, analog-mixed signal and RF. PCB design trend continues to be flat, and includes license and maintenance. The IC layout verification market is pointing to a 2.1 percent CAGR at the end of 2011. The RTL simulation market has been growing at 1.3 percent CAGR for the last decade. The IC physical implementation market has been growing at 3,4 percent CAGR for the last decade.
Growth areas in EDA from 2000-2011 include DFM at 28 percent CAGR, formal verification at 12 percent, ESL at 11 pecent, and IC/ASIC analysis at 9 percent, respectively.
What will generate the next wave of electronic product design challenges, and the future growth of EDA? This would involve solving new problems that are not part of the traditional EDA, and ‘do what others don’t do!
Methodology changes that may change EDA
There are five factors that can make this happen. These are:
* Low power design beyond RTL (and even ESL).
* Functional verification beyond simulation.
* Physical verification beyond design for manufacturability.
* Design for test beyond compression.
* System design beyond PCBs
Low power design at higher levels
Power affects every design stage. Sometimes, designing for low power at system level is required. System level optimization has the biggest impact on power/performance. And, embedded software is a major point of leverage.
Embedded software has an increasing share of the design effort. Here, Mentor’s Nucleus power management framework is key. It has an unique API for power management, enables software engineers to optimize power consumption, and reduces lines of application code. Also, power aware design optimizes code efficiency.
Functional verification beyond RTL simulation
The Verification methodology standards war is over. UVM is expected to grow by 286 percent in the next 12 months. Mentor Graphics Questa inFact is the industry’s most advanced testbench automation solution. It enables Testbench re-use and accelerates time-to-coverage. Intelligent test bench facilitates linear transition to multi-processing.
Questa accelerates the hardware/software verification environment. In-circuit emulation has been evolving to virtual hardware acceleration and embedded software development. Offline debug increases development productivity. A four-hour on-emulator software debug session drops to 30 minutes batch run. The offline debug allows 150 software designers to jumpstart debug process on source code. Virtual stimulus increases the flexibility of the emulator. As an example, Veloce is 700x more efficient than large simulation farms.
Physical verification beyond design for manufacturability
The Calibre PERC is a new approach to circuit verification. The Calibre 3DSTACK is the verification flow for 3D.
Singapore based Plunify claims that chip design companies can design faster and better using cloud computing. Stressing on the company’s go-to-market strategy, Plunify’s founder, Harn Hua Ng, said the Plunify partners with tool vendors, their distributors and complementary sales representatives.
Since pay-as-you-go business models are rare in the semiconductor industry, we went through several steps, of which the first was to better understand the market, the available tools and stake-holders:
* How is the market reacting to cloud computing and licensing schemes?
* What are current tool capabilities with regards to multiple CPUs/servers? Which parts of the chip design workflow can best take advantage of scalable, parallel features?
* What tools are more suitable for a cloud environment?
With these in mind, the next step was to build the cloud platform and the application clients to address immediate concerns – security, accessibility and cost.
“Then, we partner with tool vendors, their distributors and sales reps to bring our solutions to end-users. Companies of different sizes
view the advantages of cloud computing differently, so solutions need to be customized accordingly. Some see Plunify as solving longer term IT problems of scaling and provisioning; while others use us as an immediate way to speed up their design workflows. We are still in the process of learning about the market.”
How can the on-demand cloud computing platform dramatically accelerate chip design workflows? According to Harn Hua Ng, one immediate benefit is an almost instantaneous fulfillment of peak demand IT requirements, for example, a urgent request to do 100 synthesis builds to fix a problem due yesterday. Or if the problem cannot be fixed, at least the design team will find out in a day rather than potentially in three months’ worth of runtime without a cloud solution. The longer term acceleration is a gradual parallelization of the design workflow.
Currently, chip designers tend to visualize the design workflow as a chain of mostly serial steps with many dependencies, just because many steps can be time-consuming (both in terms of runtime and time taken to analyze intermediate results).
With an on-demand compute platform, designers can have more room to experiment and to optimize, more readily incorporating agile practices in hardware development.
Argon Design, a leading developer of high performance software applications for manycore communications processors, launched Argon Blaster, the industry’s first flow simulation solution for generating realistic, Internet scale traffic loads and applications to test networking and security equipment.
Blaster delivers a line rate, timing accurate, flow simulation application on an affordable PCIe acceleration card for use in standard x86 platforms. This enables OEMs to cost effectively distribute a high performance simulation and traffic generation solution throughout the engineering organization. The approach significantly reduces development time and cost, while simultaneously increasing product quality.
Blaster is designed for enterprise and carrier network operators for performance testing of flow based cyber security and network analytics applications. It enables network managers to verify that these systems are designed and deployed in a manner to match expected network loads.
High performance, accuracy rule!
Elaborating on the features, Daniel Proch, director of product management, Netronome, said: “Argon Blaster is the industry’s highest-performance and most-accurate flow simulation solution, in an affordable package. Developed by Argon Design, Blaster enables a standard x86 PC with a Netronome flow processor PCIe card to generate realistic, Internet-scale traffic loads and application mixes.
“For many networking applications, the ability to classify and manage traffic flows is key to enabling the highest level of performance and scalability. Quality of Service, Load Balancing, Firewall, Intrusion Detection, Content Inspection, Data Loss Prevention and similar applications all typically require flow-aware processing capabilities and this flow-aware traffic generation solution for development and QA. Blaster is the first traffic generation tool designed specifically for flow simulation applications. With Blaster, you can emulate up to a million unique flows with accurate, consistent, per-flow rate control.”
It will be interesting to know how Blaster will help the ISVs and OEMs generate realistic, Internet-scale traffic loads and applications to test networking and security equipment.
Blaster can be installed in any modern PC running Linux. It installs as a KVM virtual machine and can be operated from within the virtual machine or externally. It replays one more multiple .pcap files and can take that traffic and emulate any type of traffic profile from that pcap(s). The user can change the # flows per pcap file, the addressing scheme (# clients and servers based on MAC and or IP address).
From this set of knobs and given a set of pcaps with appropriate application traffic to any traffic load and application mix that is desired. Organizations can then offer:
* Performance benchmarking to isolate bottlenecks.
* Stress testing with real-world loads.
* Security testing with background, application and attack traffic.
* Quality assurance with broad spectrum of application and protocols.
Let’s find out a bit more about the role played by Netronome as well as Argon Design. Proch said: “The product is an Argon branded product that is a joint development with Argon Design. Netronome provides the accelerated flow processing hardware for the solution in the form of a standard PCIe card, and Argon designed and engineered the software. Netronome will be handling sales and marketing of the product. Software and support will be handled by Argon.”
Will there be an upgrade sometime later, next year, perhaps? “Most certainly,” he continued. “Our early access customers and internal use has already developed a robust roadmap and we anticipate these features and others to be rolled out over several subsequent software releases. We also expect to have a new hardware version based on our recently announced NFP-6xxx family of flow processors when available.”
Xilinx Inc. has announced the Vivado Design Suite. It enables an IP and system centric next generation design environment. Especially meant for the next decade of ‘All-Programmable’ devices, it also accelerates the integration and implementation up to 4X. And, why now? That’s because the all-programmable devices enable programmable systems ‘integration.
There are system integration bottlenecks, such as design and IP re-use, integrating algorithmic and RTL level IP, mixing DSP, embedded, connectivity and logic, and verification of blocks and “systems”.
There are implementation bottlenecks as well, such as hierarchical chip planning, multi-domain and multi-die physical optimization, predictable ‘design’ vs. ‘timing’ closure, and late ECOs and rippling effect of changes.
Vivado accelerates productivity up to 4X. The design suite elements include an integrated design environment, has a shared scalable data model, is scalable to 100 million gates, and debug and analysis. It shares design information between implementation steps that ensures fast convergence and timing closure. This enables highly efficient memory utilization. Also, it is scalable to future families, that are greater than 10 million logic cells (100 million gates) and enables cross-probing across the entire design.
Vivado also enables packaging designs into system-level IP for re-use. You can share IP within your team, project or company. Any 3rd party IP is delivered with a common look and feel. You can re-use IP at any point in the implementation process. The IP can be source, placed, or placed and routed.