“Bangalore should become the hardware capital of India,” according to Ananth Kumar, MP and former Union minister of Urban Development. Bangalore should not only be known as the software capital and silicon valley of India. “That should be the main aim of Electronica India 2010 expo.”
“India also needs hardware parks, besides software parks,” he added. India needs hardware parks that should be more like multiplexes. He mentioned that taxation regime in Karnataka was also blocking development of electronics hardware. Hardware should also enjoy the taxation benefits that hardware enjoys, he stressed. “We should be the major exporters of hardware.”
There are several highlights from day one of Electronica India 2010. I hope you get a chance to pick up the show daily being produced by yours truly on behalf of the Global SMT & Packaging magazine, thanks to my good friend and ex-colleague Debashish Chowdhury.
Some of the highlights are:
I also met a supplier who has an e-bike. Need to catch up with him sometime soon!
It was also great to catch up with Bhupinder Singh and Sunali Agarwaal of MMI India, Anil Kumar of IPCA, as well as Ranga Prasad of Aqtronics, and several other folks, who, up until now, were merely friends over email or telephone.
More later, time permitting!
I had mixed feelings on reading a press release on the recommendations from the Task Force set up by the Ministry of Communications & IT, Government of India in August 2009 to suggest measures to stimulate the growth of IT, ITeS and electronics hardware manufacturing in the country. However, I was quite surprised to see a news suggesting an amendment of the Indian semiconductor policy!
First, the Task Force’s recommendations. I’ll only focus on the electronics manufacturing bit! For electronics system design and manufacturing — it suggests the following:
* Establishing a ‘National Electronics Mission’ -– a nodal agency for the electronics Industry within DIT and with direct interface to the Prime Minister’s Office (PMO). The nodal agency would help in the synchronized functioning of the Industry through effective coordination across Ministries and Government Departments in the Centre and the States and would enhance the ease of doing business.
* Nurturing established electronics manufacturing clusters and develop them into centres of excellence, while encouraging new ones.
Isn’t this old wine in new bottles? Also, have we really done enough in the past to even boost electronics hardware manufacturing in the country? If yes, then where are the mini Hsinchus and Shenzhens within India? Even N. Vittal had said something similar (such as developing mini Hong Kongs and Singapores) some years ago!
India already has an Electronics Hardware Technology Park (EHTP) scheme. The business of establishing key electronics manufacturing clusters and developing them into centres of excellence — while encouraging new ones — should have been taken care of much, much earlier! By much. much earlier — at least 10-15 years ago!
By the time the Task Force’s recommendations are acted upon, a year or two more would have easily passed! That stretches the manufacturing gap even further!
Let me ask one question: how well is India known globally for its local telecom manufacturing companies, or, even hardware manufacturing companies? Why am I asking this question? Well, when the National Telecom Policy was announced back in 1994. Many would recall there were a lot of astronomical bids — especially the ones from Himachal Futuristic. What many overlook is the fact that the period actually presented a brilliant opportunity before India to become a leader in telecom and electronics hardware manufacturing! However, that hasn’t and never quite happened!
The Indian electronic components story is more or less the same! India’s electronic components and accessories ecosystem industry is currently moderate. It used to be 15 percent and has now grown to 35 percent. This should be grown even further! Are we backing the electronic components segment enough?
What sort of guidance or hand holding will be provided to those firms who look to develop India-based product companies? For that matter, how many great software products have been conceptualized, designed and developed in India that are worth mentioning?
Further, an interesting fact brought up time and again within the Indian industry is the requirement of a robust entrepreneurial spirit, and the need for much more sources of funding for semiconductor product companies. Who all are helping the Indian semicon startups?
And then, there’s this news that suggests amending the existing Indian semiconductor policy! It is sheer bad luck that silicon IC fabs haven’t happened in India, as yet! Although HSMC and SemIndia started off with good intentions, things got sidetracked due to various reasons. Now, solar PV has attracted several players. It was also part of the semicon policy, isn’t it? So, where is the question of amending the policy?
Yes, there is definitely a need to develop strong entrepreneurial spirit within the country and encourage local product development, rather than remain contented with a services-oriented mindset and industry.
Last July, during the ISA Excite, there was an announcement that Karnataka would have its semicon policy soon. It hasn’t happened yet, but I hope it will!
Nevertheless, here’s what I wrote last year on what India brings to the semicon world (and Japan), as I attempted to answer this question from a friend:
What are India’s strengths?
The clear strengths of the Indian semiconductor industry are embedded and design services! We are NOT YET into product development, but one sincerely hopes that it gathers pace.
The market drivers in India are mobile phone services, IT services/BPO, automobiles and IT hardware. India is also very strong in design tools, system architecture and VLSI design, has quite strong IP protection laws, and is reasonably strong in concept/innovation in semiconductors.
Testing and packaging are in a nascent stage. India will certainly have more of ATMP facilities. Nearly every single semicon giant has an India presence! That should indicate the amount of interest the outside world has on India. In fact, I am told, some key decisions are now made out of the Bangalore based outfits!
I had also suggested a 10-point program for the Karnataka semicon policy — in another blog post — on June 29, 2008. The points were:
1. A long-term semiconductor policy running 20-25 years or so.
2. Core team of top Indian leaders from Indian firms and MNCs, as well as technology institutes in Karnataka to oversee policy implementation.
3. Incentives such as government support, including stake in investments, and tax holidays.
4. Strong infrastructure availability and management.
5. Focus on having solar/PV fabs in the state.
6. Consider having 150/180/200mm fabs that tackle local problems via indigenous applications.
7. Develop companies in the assembly testing, verification and packaging (ATMP) space.
8. Attract companies in fields such as RFID, to address local problems and develop local applications.
9. Pursue companies in PDP, OLED/LED space to set up manufacturing units.
10. Promote and set up more fabless units.
There should be some steps to create specific zones for setting up such units — for fabs, fabless, ATMP, manufacturing, etc., all spread equally across the state.
Well, can’t all of this be extended across the country, rather than Karnataka alone? It sure can! What wasn’t done earlier, should be done now. Better late than never!
There’s also a lack of funding for certain semicon and hardware manufacturing areas/projects. This is another aspect that needs to be looked into.
As I’ve mentioned time and again to some friends within the Indian semiconductor industry and solar /PV industry — the semicon policy (earlier), and the National Solar Mission (now), are meant to help you guys! It is up to you — the industry folks — to make things happen! If you don’t, who will?
I am sure that the Task Force’s recommendations are very well thought out and quite robust. I don’t have the luxury of reading a copy, barring the release, and so there’s nothing for me to add. Best wishes to the Indian electronics hardware manufacturing industry and may it succeed greatly in future.
Following the success of India’s semiconductor policy, the government of India is well on its way to announce a new hardware manufacturing policy, hopefully sometime this month.
According to M. Madhavan Nambiar, Additional Secretary, Ministry of Communications & Information Technology, Department of Information Technology, the hardware policy should be coming shortly, where, the government is looking to address infrastructure related issues.
Speaking with him on the sidelines of the Thought Leader Series organized by the India Semiconductor Association (ISA), he said the hardware policy would still take some time. “As a part of it, we are looking at IT investment regions.” These would be set up in 40km areas, and each region would be an entire ecosystem in itself.
Nambiar added: “We are also looking at very good public-private partnerships. We have to develop the manpower.” The Department is working with the Labour Ministry and other organizations in order to set up skill development units. It is necessary for skiils to keep pace with technology.
The to-be-announced hardware policy will also be looking at taxes, etc. “It is a recommendation that we are making,” he said. “For India to be able to attract investments, we nust ensure that we are the best in class.”
Touching upon the semiconductor policy, he said it was important that this policy was pro-active and friendly. “We need to see how best to provide comfort levels to those investing,” Nambiar said.
It was necessary to have a strong semiconductor industry in India, as all leading countries, such as the USA, China, Taiwan and Japan had equally strong semiconductor industries. There has since been lot of interest in fabs and ecosystem units, and some of those were in the process of being set up.
According to Dr. Walden C. Rhines, chairman and CEO, Mentor Graphics Corp., verification has to improve and change every year just to keep up with the rapidly changing semiconductor technology. Fortunately, the innovations are running ahead of the technology and there are no fundamental reasons why we cannot adequately verify the most complex chips and systems of the future. He was speaking at the recently held DVCON 2014 in Bangalore, India.
A design engineer’s project time for doing design has reduced by 15 percent from 2007-2014, while the engineer’s time for doing verification had seen 17 percent increase during the same time. At this rate, in about 40 years, all of a designer’s time will be devoted to verification. At the current rate, there is almost no chance of getting a single-gate design correct on first pass!
Looking at a crossover of verification engineers vs. designer engineers, there is a CAGR designers of 4.55 percent, and for CAGR verifiers, it is 12.62 percent.
The on-time completion remains constant, as we look at the non-FPGA project’s schedule completion trends, which are: 67 percent behind schedule for 2007, 66 percent behind schedule for 2010, 67 percent behind schedule for 2012, and 59 percent behind schedule for 2014. There has been an increase in the average number of embedded processors per design size, moving from 1.12 to 4.05.
Looking at the macro trends, there has been standardization of verification languages. SystemVerilog is the only verification language growing. Now, interestingly, India leads the world in SystemVerilog adoption. It is also remarkable that the industry converged on IEEE 1800. SystemVerilog is now mainstream.
There has been standardization in base class libraries as well. There was 56 percent UVM growth between 2012 and 2014, and 13 percent is projected growth in UVM the next year. Again, India leads the world in UVM adoption.
The second macro trend is standardization of the SoC verification flow. It is emerging from ad hoc approaches to systematic processes. The verification paradox is: a good verification process lets you get the most out of best-in-class verification tools.
The goal of unit-level checking is to verify that the functionality is correct for each IP, while achieving high coverage. Use of advanced verification techniques has also increased from 2007 to 2014.
Next, the goal of connectivity checking is to ensure that the IP blocks are connected correctly, a common goal with IP integration and data path checking.
The goal of system-level checking is performance, power analysis and SoC functionality. Also, there are SoC ‘features’ that need to be verified.
A third macro trend is the coverage and power across all aspects of verification. The Unified Coverage Interoperability Standard or UCIS standard was announced at DAC 2012 by Accellera. Standards accelerate the EDA innovation!
The fourth trend is active power management. Now, low-power design requires multiple verification approaches. Trends in power management verification include things like Hypervisor/OS control of power management, application-level power management, operation in each system power state, interactions between power domains, hardware power control sequence generation, transitions between system power states, power domain state reset/restoration, and power domain power down/power up.
Macro enablers in verification
Looking at the macro enablers in verification, there is the intelligent test bench, multi-engine verification platforms, and application-specific formal. The intelligent test bench technology accelerates coverage closure. It has also seen the emergence of intelligent software driven verification.
Embedded software headcount surges with every node. Clock speed scaling slows the simulation performance improvement. Growing at over 30 percent CAGR from 2010-14, emulation is the fastest growing segment of EDA.
As for system-level checking, as the design sizes increase emulation up, the FPGA prototyping goes down. The modern emulation performance nmakes virtual debug fast. Virtual stimulus makes emulator a server, and moves the emulator from the lab to the datacenter, thereby delivering more productivity, flexibility, and reliability. Effective 100MHz embedded software debug makes virtual prototype behave like real silicon. Now, integrated simulation/emulation/software verification environments have emerged.
Lastly, for application-specific formal, the larger designs use more formal. The application-specific formal includes checking clock domain crossings.
DVCon India 2014 has come to Bangalore, India, for the first time. It will be held at the Hotel Park Plaza in Bangalore, on Sept. 25-26. Dr. Wally Rhines, CEO, Mentor Graphics will open the proceedings with his inaugural keynote.
Gaurav Jalan, SmartPlay, chair – promotions committee took time to speak about DVCon 2014 India.
Focus of DVCon 2014 India
First, what’s the focus of DVCon 2014 India? According to Jalan, DVCon has been a premiere conference in the US contributing to quality tutorials, papers and an excellent platform for networking. DVCON India focuses on filling the void of a vendor neutral quality conference in the neighbourhood – one that will grow over time.
The idea is to bring together, hitherto dispersed, yet substantial, design, verification and ESL community and give them a voice. Engineers get a chance to learn solutions to the verification problems, share the effectiveness of the solutions they have experimented, understand off the shelf solutions that are available in market and meet the vendor agnostic user fraternity. Moving forward the expectation is to get the users involved as early adopters of upcoming standards and actively contribute to them.
Trends in design
Next, what are the trends today in design? Jalan said while the designs continue to parade on the lines of Moore’s law there is a lot happening beyond the mere gate count. Defining and developing IPs with a wide configuration options serving a variety of application domains is a challenge.
The SoCs are crossing multi billion gate design (A8 in iPhone6 is 2 billion) with multi-fold increase in complexity due to multiple clock domains, multiple power domains, multiple voltage domains while delivering required performance in different application modes with sleek foot print.
Trends in verification
Now, let’s examine the trends today in verification. When design increases linearly, verification jumps exponentially. While UVM has settled dust to some extent on the IP verification level, there is a huge of challenges still awaiting to be addressed. The IP itself is growing in size limiting the simulator and encouraging users to move to emulators. While UVM solved the methodology war the VIPs available are still not simulator agnostic and expecting a emulator agnostic VIP portfolio is still a distant dream.
SoC verification is still a challenge not just due to the sheer size but because porting an env from block to SoC is difficult. The test plan definition and development for SoC level itself is a challenge. Portable stimulus group from Accellera is addressing this.
Similarly, coverage collection from different tools is difficult to merge. Unified coverage group at Accellera is addressing this. Low power today is a norm and verifying a power aware design is quite challenging. UPF is an attempt to standardize this.
Porting a SoC to emulator to enable hardware acceleration so as to run usecases is another trend picking up. Teams now are able to boot android on an SoC even before the silicon arrives. With growing analog content on chip the onus is on the verification engineers to ensure the digital and analog sides of the chip work in conjunction as per specs. Formal apps have picked so as to address connectivity tests, register spec testing, low power static checks and many more.
Accelearating EDA innovation
So, how will EDA innovation get accelerated? According to Jalan, the semiconductor industry has always witnessed that startups and smaller companies lead the innovation. Given the plethora of challenges around, there are multiple opportunities to be addressed from both the biggies and the start-ups.
The evolution of standards at Accellera definitely is a great step so as to bring the focus on real innovation in the tools while providing a platform for the user community to come forward sharing the challenges and proposing alternates. With a standard baseline that is defined with collaboration from all partners of the ecosystem, the EDA companies can focus on competing on performance, user interface, increased tool capacity and enabling faster time to market.
Forums like DVCON India help in growing awareness on standard promoted by Accellera while encouraging participants from different organizations and geographies join to contribute. Apart from tools areas where EDA innovation would pick up include new IT technologies and platforms – Cloud, Mobile devices.
Next level of verification productivity
Where is the next level of verification productivity likely to come from? To this, Jalan replied that productivity in the verification improves from different aspects.
While faster tools with increased capacity comes from innovation at EDA end, standard have played an excellent role in addressing it. UVM has helped in displacing vendor specific technologies to improve inter-operability, quick ramp up for engineers and reusability. Similarly on power format, UPF has played an important role in bridging the gaps.
Unified coverage is another aspect where it will help in closing early with coverage driven verification. IPXACT and SystemRDL standards help further in packaging IPs and easier hand off to enable reuse. Similarly other standards on ESL, AMS etc help in closing the loop holes that prevent productivity.
New, portable stimulus specification now being developed under Accellera that will help in easing out test development at different levels from IP to sub system to SoC. For faster simulations, the increase in adoption of hardware acceleration platforms is helping verification engineers to improve regression turn around time.
Formal technologies play an important role in providing a mathematical proofs to common verification challenges at an accelerated pace in comparison to simulation. Finally events like DVCON enables users to share their experiences and knowledge encouraging others to try out solutions instead of struggling with the process of discovering or inventing one.
More Indian start-ups
Finally, do the organizers expect to see more Indian start-ups post this event? Yes, says Jalan. “We even have a special incubation booth that is encouraging young startups to come forth and exhibit at a reduced cost (only $300). We are creating a platform and soon we will see new players in all areas of Semiconductor.
“Also, the Indian government’s push in the semiconductor space will give new startups further incentive to mushroom. These conferences help entrepreneurs to talk to everyone in the community about problems, vet potential solutions and seek blessings from gurus.”
My dear friends, I am now in the process of selling off Pradeep’s Point! as well as all of my other blogs! 🙂
As most of you are probably aware, Webstatsdomain.org estimated Pradeep’s Point! at a whopping $19.1 billion in July 2014. As I write this post, the number has slightly reduced to $16.6 billion. Pradeep’s Point! is my flagship blog! 😉
It’s been a long time! I started Pradeep’s Point! back in 2007, having just returned to India after my second stint in Hong Kong and China. Actually, it was initially placed under Blogspot as Pradeep Chakraborty’s Blog – when it won the first international award – Pradeep Chakraborty’s Blog was selected as the best in the world in the Electronic Hardware category for 2008-10, by Electronics Weekly, UK. I remember and would again like to thank all of those folks who voted for me to the first ever international title! 🙂
Next, Pradeep Chakraborty’s Blog received an Honorable Mention @ Blognet Awards 2009! That’s also the time when someone succeeded in adding malware to that blog, and there was absolutely no fault of mine, and it was later removed by Google! I recall spending an entire night migrating the content to WordPress, where I had a secondary blog – Pradeep’s Point!
I moved on to WordPress, migrated all of the posts, and Pradeep’s Point! was reborn, or rather, born!
Thereafter, it has been hugely satisfying journey for me! I managed to pick up at least one international award / international recognition for all of my blogs, every year, till this year! 😉 These are:
* PC’s Semicon Blog awarded the Top Digital Media Blog by Online IT Degree (in November 2010).
* Green Gadget of Texas, USA, awarded Pradeep’s Point! as the “Featured Tech Site” for 2011!
* In 2012, Gorkana, UK, selected Pradeep’s Point! as the Blog Influencer 2012!
* PC’s Telecom Blog listed among Best VoIP blogs by HostedSwitch, USA.
* In Feb. 2013, PC’s Electronic Components Blog selected as 100 Top Resources for Electrical Engineers on ElectricalEngineeringSchools.org, USA.
* In August 2014, PC’s Electronic Components Blog was ranked 11th in the “Top 101 Best Resources for Electrical Engineers.”
Now, this year, the huge estimation of Pradeep’s Point! by Webstatsdomain.org! 🙂
As I write, two folks – from Bangalore — are trying to gather funds to buy Pradeep’s Point! Although, my personal preference is for a very good friend! 🙂
The other five blogs up for sale are:
* PC’s Semiconductors Blog. (Won an award)
* PC’s Solar Photovoltaics Blog.
* PC’s Electronics Blog.
* PC’s Electronic Components Blog. (Won two awards)
* PC’s Telecom Blog. (Won an award)
I hope that the blogs will all remain, as will the content, but the owner (or owners) will be different! Perhaps, the blogs could have a different name!
Maybe, the new owners will try and keep me on board, too! 😉 (I hope, they do).
I already have feelers, again from Bangalore, for buying out PC’s Semiconductors Blog and PC’s Electronic Components Blog. Again, I would prefer, if a friend, hopefully, tried to buy all of them, together! One blog definitely can’t do without the other – that’s my estimation! 😉 Well, let’s see what happens!
So, my dear friends, once again, it has been a pleasure serving you all via my blogs! Now, they are in the process of being sold off. Whoever buys those, will definitely have a great future! 🙂 (In case, I change my mind, the blogs will remain as they are! 😉 )
About time 😉 I guess!! Thanks everyone, for your tremendous love and continuous support! 🙂
“I’d rather attempt to do something great and fail, than to attempt to do nothing and succeed!” — Robert H. Schuller.
Yes, I definitely agree! 🙂
The EDA 360 was an industry vision. It reflected a change in market requirements. It was application driven system design. From a Cadence perspective, the company has done system design enablement, according to Nimish Modi, senior VP, marketing and business development, Cadence Design Systems Inc.
In Apple’s case, the iOS is unique. Cadence feels that the heart of the design is the SoC. The electrical analysis is becoming very important. For instance, how do you optimize before tape-out? Hardware and software conversion presents a huge problem as well. The IP plays an important part. Cadence did IP-as-a-service. It now has an IP strategy.
Today, EDA is about possibility, not productivity. Cadence provides tools and content for semiconductor and systems companies. It is now realizing the EDA 360 vision.
According to Modi, each IP is immensely complex. Standards based or interface IP is not enough! Silicon-proven design is the need of the hour. Now, more and more IP blocks are said to be coming together.
Cadence is offering the Palladium XP, and its primary use is for system verification. Software development is becoming a little bit difficult. People are providing software prototypes. The Palladium compile, turnaround and debug are very fast, best-in-class. All memory, clocking, partitioning, etc., is now automated.
The capacity of the Protium platform is 100 million gates. It will enable hardware and software developers. The use model for Protium is:
* Hardware folks use it for hardware regression.
* Software folks use it for early software development.
The main value proposition is the faster bring-up time. Also, the Palladium hybrid model helps customers overcome the boot problem. It is a hybrid of emulation and virtual prototyping. The dynamic power analysis is another issue. The Palladium hybrid model helps to do the testing.
Collaboration with ARM
ARM provides processor IPs. Cadence works closely with ARM. Cadence is also co-optimizing its tools to provide the best PPA. Physical libraries and tools get optimized. Cadence’s tools are optimized for ARM architecture. Cadence is also the first ones on the access to the V8 ARM models.
Renesas Electronics recently opened its India subsidiary in Bangalore. Elaborating, Sunil Dhar, managing director of Renesas Electronics India said: “We are glad to announce the opening of Renesas Electronics India Pvt Ltd, a wholly-owned subsidiary of Renesas Electronics Singapore Pte Ltd., located in Bangalore.
“Since 2010, Renesas has been providing technical product support to its customers here via branch offices in Bangalore, Delhi and Mumbai. As part of its expansion plan, Renesas will turn our said branches into a full subsidiary.
“The branch office setup served us well when the organization was small and its role was limited. In order to expand further in terms of opening more offices in India for close customer support, and to be able to provide wider services to customers in India like reference software, hardware, reference solutions which would be developed in India, it would require us to have a permanent establishment here.
“Through this new company, we aim to expand business by providing the best solution offerings and technical support as well as a regional systems solution development expertise to the Indian market.”
How does the India R&D team play a role in global innovation and where do you see Renesas Electronics in India five years from now?
He said that over 50 percent of the Renesas India team is application development or field engineers armed with knowledge of embedded hardware and software development and support.
In order to expand the footprint in Indian markets, Renesas plans to build up a strong application engineering team. India Application engineering team will engage with the Renesas headquarters, regional offices to develop new products and solutions dedicated for emerging countries, including India.
The application engineering team and the future solution centre aim to survey the market for solution needs, prepare India designed solutions fitting the price points and specifications points as required in the Indian market. Along with the customers, the team also intends to collaborate with the design houses to create innovative solutions addressing upcoming needs of the market. Our goal is to become the most trusted semiconductor solution provider in India.
What are the India-centric solutions that would be developed from the India Application Engineering team?
Dhar added that the needs of emerging markets are usually different in both specifications as well as price points. By providing dedicated local support via the new company, and with a focus on industrial and automotive applications for two- and four-wheelers, Renesas aims to increase its MCU share in India and expand its solution offerings with rich lineup of kit solutions (MCU + SoC + power devices) and platform reference boards (boards with complete ecosystem including devices and software) to provide customers a shorter time-to-market.
The team will initially focus on automotive and particularly, two-wheeler solutions. The intention is to expand the scope of the application engineering team’s activity to industrial and consumer appliances in near term.
What is the overall India employee strength? How are the investment plans looking up?
Dhar said: “In order to expand our footprint in Indian markets, we will double our headcount in near term. Currently, we are just under 30 staff and over 50 percent of us are application development or field engineers armed with the knowledge of embedded hardware and software development and support. Upon setting up the organization in Sales and Marketing roles in the initial days, we also have plans to announce the setting up of a Solutions Centre in India to develop reference application solutions to enable our customers to use our devices.
“We are intending to invest in lab, infrastructure setup and expansion of activities in the next three to five years. Additionally, we are also considering investing towards 3rd party and IDH for enlarged business engagement.”
Trends driving automotive market in India
Regarding trends driving the automotive market in India, Dhar said that Renesas focusses on three business segments – automotive, industrial and home, OA and ICT. Renesas holds more than 40 percent global market share for automotive MCU business. Our target applications for automotive segment are automotive control and automotive infotainment and network.
Renesas has dedication applications solutions for integrated cockpit through system on chip, R-car ecosystem collaboration solution for e-mobility and automotive analog and power devices for driving, steering and braking.
As semiconductor technologies evolved, it has enabled automakers to integrate multiple applications on a single chip significantly reducing the board area; thus optimizing performance and adding new features for comfort, safety and infotainment. Power technologies have brought energy efficiency, limiting power consumption in vehicles. Advancements in process technologies will continue to drive the auto industry in the coming years.
Renesas, for instance, developed the industry’s first 28nm flash memory IP for MCUs and the first semiconductor supplier to move from 40nm to 28nm process technology.
“Trends driving auto industry in India and globally are more of less the same. However, for India market, we see a specific demand for two-wheeler solutions and that is our target in coming years,” he concluded.
Lastly, I must take the opportunity to thank Ms Shweta Dhadiwal-Baid and Ms Sharmita Mandal for making this happen! 😉