Future Horizons hosted the 22nd Annual International Electronics Forum, in association with IDA Ireland, on Oct. 2-4, 2013, at Dublin, Blanchardstown, Ireland. The forum was titled ‘New Markets and Opportunities in the Sub-20nm Era: Business as Usual OR It’s Different This Time.” Here are excerpts from some of the sessions. Those desirous of finding out much more should contact Malcolm Penn, CEO, Future Horizons.
The global interest in graphene research has facilitated our understanding of this rather unique material. However, the transition from the laboratory to factory has hit some challenging obstacles. In this talk I will review the current state of graphene research, focusing on the techniques which allow large scale production.
I will then discuss various aspects of our research which is based on more complex structures beyond graphene. Firstly, hexagonal boron nitride can be used as a thin dielectric material where electrons can tunnel through. Secondly, graphene-boron nitride stacks can be used as tunnelling transistor devices with promising characteristics. The same devices show interesting physics, for example, negative differential conductivity can be found at higher biases. Finally, graphene stacked with thin semiconducting layers which show promising results in photodetection.
I will conclude by speculating the fields where graphene may realistically find applications and discuss the role of the National Graphene Institute in commercializing graphene.
The key challenge for future high-end computing chips is energy efficiency in addition to traditional challenges such as yield/cost, static power, data transfer. In 2020, in order to maintain at an acceptable level the overall power consumption of all the computing systems, a gain in term of power efficiency of 1000 will be required.
To reach this objective, we need to work not only at process and technology level, but to propose disruptive multi-processor SoC architecture and to make some major evolutions on software and on the development of
applications. Some key semiconductor technologies will definitely play a key role such as: low power CMOS technologies, 3D stacking, silicon photonics and embedded non-volatile memory.
To reach this goal, the involvement of semiconductor industries will be necessary and a new ecosystem has to be put in place for establishing stronger partnerships between the semiconductor industry (IDM, foundry), IP provider, EDA provider, design house, systems and software industries.
This presentation looks at the development of the semiconductor and electronics industries from an African perspective, both globally and in Africa. Understanding the challenges that are associated with the wide scale adoption of new electronics in the African continent.
Electronics have taken over the world, and it is unthinkable in today’s modern life to operate without utilising some form of electronics on a daily basis. Similarly, in Africa the development and adoption of electronics and utilisation of semiconductors have grown exponentially. This growth on the African continent was due to the rapid uptake of mobile communications. However, this has placed in stark relief the challenges facing increased adoption of electronics in Africa, namely power consumption.
This background is central to the thesis that the industry needs to look at addressing the twin challenges of low powered and low cost devices. In Africa there are limits to the ability to frequently and consistently charge or keep electronics connected to a reliable electricity grid. Therefore, the current advances in electronics has resulted in the power industry being the biggest beneficiary of the growth in the adoption of electronics.
What needs to be done is for the industry to support and foster research on this subject in Africa, working as a global community. The challenge is creating electronics that meet these cost and power challenges. Importantly, the solution needs to be driven by the semiconductor industry not the power industry. Focus is to be placed on operating in an off-grid environment and building sustainable solutions to the continued challenge of the absence of reliable and available power.
It is my contention that Africa, as it has done with the mobile communications industry and adoption of LED lighting, will leapfrog in terms of developing and adopting low powered and cost effective electronics.
Personalized, preventive, predictive and participatory healthcare is on the horizon. Many nano-electronics research groups have entered the quest for more efficient health care in their mission statement. Electronic systems are proposed to assist in ambulatory monitoring of socalled ‘markers’ for wellness and health.
New life science tools deliver the prospect of personal diagnostics and therapy in e.g., the cardiac, neurological and oncology field. Early diagnose, detailed and fast screening technology and companioning devices to deliver the evidence of therapy effectiveness could indeed stir a – desperately needed – healthcare revolution. This talk addresses the exciting trends in ‘PPPP’ health care and relates them to an innovation roadmap in process technology, electronic circuits and system concepts.
Future Horizons recently organized and held the 21st Annual Electronics Forum on Oct. 3-5 at Bratislava, Slovakia. Here are excerpts from some of the proceedings:
Mojy Chian, senior VP Design Enablement. GlobalFoundries presented on ‘Foundry 2.0: The Era of Collaborative Device Manufacturing.’: Despite some predictions to the contrary, the foundry-based fabless model is not going away, and moreover it is driving manufacturers and device designers closer together. But like all living organisms, especially those in electronics, we have to continue to evolve. There are warning signs, both technical and economic, emerging in the foundry business that warrant our attention, and in fact require a re-thinking of how best to apply our resources and energy.
Recent talks of fabless companies investing in their own fabs, and of foundries developing ‘single company fabs’ underscore the sense of urgency. Clearly, we must change – Call it Foundry 2.0! This will be driven, ironically, by a move toward a more IDM-like model. Strategic collaboration that creates a ‘virtual IDM-like interface’ to chip design companies will help further close the gap between process teams at the manufacturing companies and design teams at the fabless companies.
With daunting technical challenges like 3D stacking, 450mm fabs, new transistor architectures, multipatterning, and the long-term viability of extreme ultraviolet (EUV) lithography, collaboration – early, often and deep – is really the only practical approach given the cost and complexities involved.
John Lofton Holt. founder, and chairman of the Board of directors. Achronix, presented on “Embedded FPGAs – Enabling The Next Generation Of Flexible SoCs.’: The system-on-chip (SoC) ecosystem is at a fundamental crossroads. With total
chip development and manufacturing costs exceeding $100 million at 22nm, it is no longer cost effective for most SoC designers to build a discrete chip for every application. As a result, SoC designers are investing in programmable intellectual property (IP) for IO expansion, emerging standards compliance and application acceleration.
This programmable IP ranges from microcontrollers and processors to simple state machines that are register-programmable. Nearly every SoC built today has some kind of programmable IP. The programmable logic industry is addressing this SoC challenge in a different way. Coming from the “other end of the spectrum”, the major public FPGA manufacturers are implementing more and more hard IP on their dies to reduce the area penalty of the programmable logic for specific applications.
These techniques, while effective for some mid-range volume applications, will not scale to high volume SoCs. The major public FPGA companies are also very hesitant to license their programmable fabric to SoC designers, fearing competition in their core markets and erosion of margins.
Rudy Lauwereins, VP Smart Systems Technology Office, IMEC, presented on ‘Providing “Insite” In The Unknown Design Space’: As technology scaling nears the “final frontier”, designers are confronted with an increasing number of restrictions.
Printing smaller and smaller features remains possible, but requires more and more regular layout patterns. Transistors can still be reduced in size, but may fall short of meeting electrical specifications. Smaller wires are becoming a performance bottleneck.
As technology scaling becomes less ideal, established design paradigms start to break. Creative and innovative solutions are required to sustain the momentum of Moore’s law: hitting the sweet-spot for cost and performance requires tight interaction between the technology development community and the design community. In an increasingly fabless world, imec’s Insite program builds the bridges between these communities.
The last decade heralded a dramatic transformation in supply chain dynamics, driven by the complexity challenge of staying on the More Moore curve. On the demand side, the high cost of fabs persuaded almost all integrated device manufacturers (IDMs) to use foundries for their leading-edge wafer supply.
The ever-increasing process complexity and its negative impact on manufacturing yields forced the adoption of sophisticated foundry-specific design-for manufacturing (DFM) techniques, effectively committing new chip designs to a single foundry and process.
At the same time, the industry adopted a much more cautious lagging rather than leading demand approach to new capacity expansion, resulting in under-supply and shortages in leading-edge wafer fab capacity. To make matters worse, the traditional oxide-based planar transistor started to misbehave at the 130nm node, as manifested by low yields and higher than anticipated power dissipation, especially when the transistors were supposed to be off, with no increase in performance, heralding the introduction of new process techniques (e.g., high-k metal gates).
Even before these structural changes have been fully digested, supply chain dynamics have been further disrupted by the prospective transition to 450mm wafer processing, to extreme ultra violet (EUV) lithography, and from planar to vertical transistor design.
Since the start of the industry, adding more IC functionality while simultaneously decreasing power consumption and increasing switching speed—a technique fundamentally known as Moore’s Law—has been achieved by simply making the transistor structure smaller. This worked virtually faultlessly down to the 130nm node when quite unexpectedly things did not work as planned. Power went up, speed did not improve and process yields collapsed. Simple scaling no longer worked, and new IC design techniques were needed.
While every attempt was made to prolong the life of the classic planar transistor structure, out went the polysilicon/silicon dioxide gate; although this transition was far from plain sailing, in came high-k metal gates spanning 65nm-28nm nodes. Just as the high-k metal gate structure gained industry-wide consensus at 28nm, it too ran out of steam at the 22nm-16nm nodes, forcing the introduction of more complex vertical versus planar transistor design and making the IC design even more process-dependent (i.e., foundry-dependent). Dual foundry sourcing, already impractical for the majority of semiconductor firms, will only get worse as line widths continue to shrink. Read more…
According to Malcom Penn, chairman and CEO, Future Horizons, 2010 — a barnstroming year — will likely see the global semiconductor industry grow by 31+ percent. He was delivering the company’s forecast at the ongoing 19th International Electronics Forum (IEF) 2010 in Dresden, Germany, which ends here tomorrow. He said it would take a disaster of the scale of Lehmann Brothers to derail this now!
Some of the other forecasts made by Malcolm Penn include:
* 2011: +28 percent; based on: peak of the structural cyclical boom (could stretch into 2012).
* 2012: +18 percent; based on: normal cyclical trash cycle starting 2H-2012 (1H-2013?).
* 2013: +3 percent based on: market correction in full flow (could be negative, cap ex overspend and inventory build depending).
* 2014: +12 percent; based on: start of the next cyclical recovery (single digit, if 2013 is negative).
The forecast track record of Future Horizons is quite interesting. As per forecasts made during the IFS2010 in Jan.2010, the chip fundamentals was said to be in very good shape. The industry was starting its recovery with shortages. Also, the ASPs had already stopped faling. The inventory levels were at an all-tme low. Finally, the capacity was tight, and spending, weak!
All of this added up to two years of very strong growth in prospect. Penn had said: “It doesn’t get much better than this. But, despite what the numbers say, still no-one believes beyond the next quarter! “Ah but” is still driving the industry consensus!
Industry fundamentals don’t lie — believe in them or die! The capacity famine was instigated two+ years ago — well before the crasj, today’s shortage was inevitable. The recovery dynamics will continue to strengthen. Future Horizons’ forecast is now +31 percent ~$300 billion. The next trash dynamic has still not yet triggered. It is unlikely to happen before 2011, meaning, 2012 impact. However, the economic uncertainty remains the biggest risk. Also, the global financial system is fundamentally flawed. Read more…
The big news: Intel and AMD announced a comprehensive agreement to end all outstanding legal disputes between the companies, including antitrust litigation and patent cross license disputes! What a relief!
In a joint statement the two companies commented, “While the relationship between the two companies has been difficult in the past, this agreement ends the legal disputes and enables the companies to focus all of our efforts on product innovation and development.”
As per the agreement the two companies obtain patent rights from a new five-year cross license agreement, Intel and AMD will give up any claims of breach from the previous license agreement, and Intel will pay AMD $1.25 billion. Intel has also agreed to abide by a set of business practice provisions.
AMD will drop all pending litigation including the case in US District Court in Delaware and two cases pending in Japan. AMD will also withdraw all of its regulatory complaints worldwide.
Ramkumar Subramanian, VP, Sales & Marketing, AMD India, said: “This is a historical settlement for the microprocessor industry. The settlement will set transparent ground rules for open, competitive markets, with which Intel, in full public view, has agreed to comply. Fair and open competition dictates that the best product wins and market forces prevail. I am very confident that this development will help us strengthen our market position.”
This is just the kind of news the global semiconductor industry needs! It is hopefully, on path of a major recovery after having faced the worst recession.
It is heartening to note that the two rivals have buried the hatchet and shaken hands — a plea I’ve been making via my blog posts for such a long time.
It would do both Intel and AMD a world of good to focus on their core competencies and continue to produce all of those magnificent chips that make all of our lives so easy and meaningful!
Good work guys and congratulations. May you have all the success and lead the global semiconductor industry to greater heights in the future.
Presenting excerpts of some more key presentations made on day 1 and 2, resepectively, at the recently held International Electronics Forum 2009 (IEF 2009), in Geneva, Switzerland, from Sept. 30-Oct. 2, which was held under the auspices of the Geneva Chancellerie D’Etat & Istitut Carnot CEA LETI.
May I also take this opportunity to thank Malcolm Penn, chairman and CEO, Future Horizons.
“ICT: Key For Global Competitiveness” — Enrico Villa, chairman, CATRINE
Enrico heads up the Cluster for Application and Technology Research In Europe on NanoElectronics (CATRINE) and through his organisation Europe is preparing for our future with development projects in nanotechnology, microelectronics, photonics, biotechnology and advanced materials.
Electronic and information systems are worth $87 trillion and growing, which is about 10 percent of global GDP. Such systems have penetrated all aspects of life, created millions of jobs and has been a motor of productivity growth.
Microelectronics is a key enabling technology for electronics and ICT, and as a consequence the semiconductor market grows at twice this GDP. The role of electronics will increase in the future and will have an impact in society due to its use in healthcare, aids for an aging population, easing transportation bottlenecks and lowering energy costs.
To meet these targets electronics and ICT must be affordable to the population at large – meaning that semiconductors must meet the trend of doubling performance every two years, reduce price per function by 40 percent per year and aim for R&D nearly 20 percent of sales.
In an example given public lighting is 13 percent of energy costs – a change to semiconductor LEDs can save a third of this energy. Enrico sees moving from ideas to products is one area where Europe is weak, but thankfully projects Jessi/Eureka/Catrine/Medea+ are bringing together cooperation between European players.
This has enabled European companies and universities to work together and create critical masses to make global products. This is born out in the fact that Europe has several global-sized semiconductor companies and two European equipment-material suppliers that are world leaders.
“Raising The Bar On Semiconductor R&D Management, Execution & ROI” — Ronald Collett, CEO, Numetrics Management Systems
Working with the company PRTM Ron is tasked to raise the management competence within the semiconductor industry so companies can compete in the global arena. The semiconductor industry is going through a profound change with the vertically chip companies disintegrating and outsourcing their manufacture. Headcount has fallen, there are fewer start-ups and everybody is cutting costs.
Companies that will survive are those with well differentiated products and superior product development ability. PRTM has produced an integrated framework of product development capabilities, which compares company actual performance against industry best practice and timescales.
It is a fact that 60 percent of semiconductor projects slip in time by at least one quarter and 16 percent slip by more than one year. The system allows ‘fact-based planning and decision making’ and allows management to get no surprise shortfalls in revenue or margin.
At a detailed level, the engineer can make a fact-based project cost estimation and can reliably make staffing requirements and schedules. It allows ‘what-if’ project analyses and calculates risk. The immediate impact is usually a reduction of projects, but a better time-to-market and ROI. An industry shakeout is inevitable and demands will overwhelm all, but the best.
“Building Complex Embedded Software Applications On Leading Edge Silicon” — Martin Orrell, General Manager, Multimedia Technologies, The Technology Partnership
TTP is an independent product development company involved in a wide range of products including embedded systems in medical devices, PC peripherals, MP3 players and automotive, industrial and traffic control.
Martin’s view is that one of the difficulties in embedded design is to recognise that the hardware and software boundaries tend to blur. Using software rather than hardware has its advantages, particularly where the standards and specifications have not firmed up, but software often costs more than the customer planned.
Costs can be saved by the re-use of silicon and software IP, the starting platform and roadmap, trimming the specification and through innovation. TTP has a wide range of experience and can often view a customer project from a different perspective and Martin gave a number of good examples of case studies where this was the case.
To finalise, two tips were given to product developers: More complex software does not mean higher project costs and silicon targeted for a different market can enable innovative opportunities in your own market. Read more…
Future Horizons has revised its 2009 global semiconductor industry forecast to -14 percent growth (+/- 2 percentage points). This was revealed by Malcolm Penn, Chairman & CEO, Future Horizons, while delivering the company’s forecast at the ongoing 18th International Electronics Forum (IEF) 2009 in Geneva, Switzerland, which ends here tomorrow. “He said, “It’s all about good management … only the bad times tell!”
Some of Penn’s other forecast summaries include:
* Economic recovery is said to have already started from 2H-2009.
* Further ‘50 percent’ cap ex reduction.
* Memory price recovery 2H-2009.
* Still lots Of blood on the road near-term
* Strong will get stronger as weak go to the wall.
* Watch for tight capacity starting 2H-2009.
* Crisis is the time to implement change (brings out the best and worst).
* R&D/new products/sound marketing will win (not counting pencils and scrapping the free coffee).
Outlook for 2010 and beyond
Penn also presented the company’s outlook for the global semiconductor industry for 2010 and beyond. These include:
* 2010: +19 percent based on: continuing recovery momentum (NB … this could be a lot, lot higher).
* 2011: +28 percent based on: peak of the structural cyclical boom (NB … this could stretch into 2012).
* 2012: +18 percent based on: normal cyclical market correction starting 2H-2012 (1H-2013?).
* 2013: +3 percent based on: market correction in full flow (NB … this could be negative).
The year 2014 could well see the start of the next cyclical recovery! Given the impending 2010 fab shortage, the upside for 2010-12 is said to be huge.
The 2009 forecast – how did we do so far?
First, let’s look at the 2008 forecasts:
Q4-08 Forecast (Jan): -22.5 percent, making overall Year -2.3 percent
* Q4 (Dec) Guidance: (Intel -20 percent, Nvidia -40/-50 percent, Broadcom -20percent/-23 percent. TSMC -30 percent, Others –20/-50 percent-ish
* Q4-08 Actual: -24.2 percent, making 2008 YoY -2.8 percent (both slightly worse).
Now, on to the 2009 forecasts:
* 2009 forecast (Jan): -28 percent.
* Q1 -20 percent (continuing Q4’s decline, but at a slower rate).
* Q2 -2 percent (market settling down and decline bottoming out).
* Q3 +12 percent (normal, but slightly subdued seasonal and structural growth).
* Q4 +3 percent (normal 4th quarter seasonal slowdown).
* Q1-09 Actual: -15.3 percent (better than Jan. forecast). Jan., not March, saw start of correction to Q4-08’s over-reaction.
* Q2-09 Actual: +16.9 percent (Much better than Jan. forecast). Also, Q1 (not Q2) was the trough with a strong April-June rebound.
* Q3-09 Outlook: +12 percent (No change In Jan. or Jul. forecast). The Q2 inventory correction spurt over with ‘normal’ seasonal growth.
* Q4-09 Outlook: +3 percent (No change in Jan. or Jul. forecast). The normal 4th quarter seasonal slowdown.
2009 Forecast (Jul): -14 percent (Much better than Jan. forecast/no change from Jul.). Minor downside risks (Q3 +8 percent and Q4 +2 percent. making year -16 percent). There is a significant upside potential (Q3 +16 percent and Q4 +4 percent, making year -12 percent).
What’s changed since January’s IFS2009?
According to Malcolm Penn, Future Horizons’ ‘Rose Glass’ scenario came true! He said: “We correctly forecast the pattern of the recovery. The rebound came one quarter earlier than expected.” Given below is a snapshot of what’s happened since the IFS2009 in January.
In January, the world was reeling from Q4’s unprecedented collapse with December peppered with last minute Q4 downward guidance warnings. Everyone was affected – from Intel downward, the collapse was a total meltdown and completely across the board – covering all markets and regions.
Next, there was absolutely zero visibility into the first quarter guidance. Many firms refused to even comment. Some said, “We Simply Have No Idea!” Others offered such a wide range of options that the guidance was meaningless.
The December’s WSTS results (released early Feb.) showed December (and hence, Q4) slightly worse than the Oct/Nov momentum at -24.2 percent (vs. –22.5 percent). The March’s WSTS results (released early May) showed March (and hence, Q1) slightly better than the Jan/Feb momentum.
In brief — from meltdown (Q4-08) to stabilisation (Q1-09) and rebound (Q2-09) in three quarters — even for the chip industry dynamics, this was unprecedented, said Penn.
I will be adding more here, a bit later… stay tuned!
Sasken Technolgies was earlier known as SAS and it was focusing on product development. Later, it moved on to services. Speaking about this shift, Rajiv C. Mody, chairman and CEO, said that Sasken has always been, from day one, working on both simultaneously.
Sasken initially started out in the EDA space and had one product in the simulation space. It was writing a simulator, addressing large complex designs and methods to simplify the designs. Simultaneously, Sasken was also doing a lot of services for large telecom companies in the areas of designing. This was continued and eventually, Sasken expanded in the area of telecommunications.
Subsequently, Sasken started building products in the telecom space. However, one significant difference is that anything that it does, it impacts Sasken’s customers’ top line as Sasken address the R&D side of the business.
Not so long back, Sasken were also a VLSI player. It decided to disband the design tool part of the business and focus completely on communications. Now, Sasken does a lot of business in chip design, which is part of VLSI. Today, it is among the leading providers of semiconductor design, working on all kinds of complex system-on-chip (SoC), as well as 65nm design.
Sasken has filed for 39 patents so far, of which 16 have been granted. Those remaining are in the process, and typically, once a patent has been applied for, it takes four years before being granted.
It has invested close to Rs 40 crore in R&D in 2007. In the first two quarters of this financial year, it has invested about Rs 15 corers in R&D. Sasken focuses on next-generation technologies, which would shape up the way things are to come in this new, converged world.
Mody said: “The fundamental thing driving this entire change is convergence — essentially entertainment, media, news, information — all of it being available at push medium as well as pull medium. Wireless is also playing a very significant role.”
All of these combinations are creating newer opportunities – starting with, say, for example, in the service provider-side, new billing methods have to be put in place because it’s going to be triple- and quad-play kinds of situations.
Simultaneously, on the handset side, with more and more computing power being made available, newer kinds of applications have started playing significant role. As a result, Sasken is now scanning the entire gamut to position itself and take advantage.
Sasken will continue to invest in products in the mobile handset space. It also has a significant role to play on the multimedia and the application frameworks. Mody added: “To give you an idea, for the mobile handset, direct broadcast is going to play a significant role. People are already talking about high definition (HD) on mobile. You will see all those kinds of interesting things coming about, and we will participate.”
Sasken had also acquired a Finnish firm. This acquisition has worked extremely well and its full integration has been done. Mody said: “We have significant engagements because of our presence in Finland and the capabilities that they bring, not only with the existing, but also with the new costumer base. We are thriving and this has given us the capability to do full end-to-end handset design and testing.”
DVCon India 2014 has come to Bangalore, India, for the first time. It will be held at the Hotel Park Plaza in Bangalore, on Sept. 25-26. Dr. Wally Rhines, CEO, Mentor Graphics will open the proceedings with his inaugural keynote.
Gaurav Jalan, SmartPlay, chair – promotions committee took time to speak about DVCon 2014 India.
Focus of DVCon 2014 India
First, what’s the focus of DVCon 2014 India? According to Jalan, DVCon has been a premiere conference in the US contributing to quality tutorials, papers and an excellent platform for networking. DVCON India focuses on filling the void of a vendor neutral quality conference in the neighbourhood – one that will grow over time.
The idea is to bring together, hitherto dispersed, yet substantial, design, verification and ESL community and give them a voice. Engineers get a chance to learn solutions to the verification problems, share the effectiveness of the solutions they have experimented, understand off the shelf solutions that are available in market and meet the vendor agnostic user fraternity. Moving forward the expectation is to get the users involved as early adopters of upcoming standards and actively contribute to them.
Trends in design
Next, what are the trends today in design? Jalan said while the designs continue to parade on the lines of Moore’s law there is a lot happening beyond the mere gate count. Defining and developing IPs with a wide configuration options serving a variety of application domains is a challenge.
The SoCs are crossing multi billion gate design (A8 in iPhone6 is 2 billion) with multi-fold increase in complexity due to multiple clock domains, multiple power domains, multiple voltage domains while delivering required performance in different application modes with sleek foot print.
Trends in verification
Now, let’s examine the trends today in verification. When design increases linearly, verification jumps exponentially. While UVM has settled dust to some extent on the IP verification level, there is a huge of challenges still awaiting to be addressed. The IP itself is growing in size limiting the simulator and encouraging users to move to emulators. While UVM solved the methodology war the VIPs available are still not simulator agnostic and expecting a emulator agnostic VIP portfolio is still a distant dream.
SoC verification is still a challenge not just due to the sheer size but because porting an env from block to SoC is difficult. The test plan definition and development for SoC level itself is a challenge. Portable stimulus group from Accellera is addressing this.
Similarly, coverage collection from different tools is difficult to merge. Unified coverage group at Accellera is addressing this. Low power today is a norm and verifying a power aware design is quite challenging. UPF is an attempt to standardize this.
Porting a SoC to emulator to enable hardware acceleration so as to run usecases is another trend picking up. Teams now are able to boot android on an SoC even before the silicon arrives. With growing analog content on chip the onus is on the verification engineers to ensure the digital and analog sides of the chip work in conjunction as per specs. Formal apps have picked so as to address connectivity tests, register spec testing, low power static checks and many more.
Accelearating EDA innovation
So, how will EDA innovation get accelerated? According to Jalan, the semiconductor industry has always witnessed that startups and smaller companies lead the innovation. Given the plethora of challenges around, there are multiple opportunities to be addressed from both the biggies and the start-ups.
The evolution of standards at Accellera definitely is a great step so as to bring the focus on real innovation in the tools while providing a platform for the user community to come forward sharing the challenges and proposing alternates. With a standard baseline that is defined with collaboration from all partners of the ecosystem, the EDA companies can focus on competing on performance, user interface, increased tool capacity and enabling faster time to market.
Forums like DVCON India help in growing awareness on standard promoted by Accellera while encouraging participants from different organizations and geographies join to contribute. Apart from tools areas where EDA innovation would pick up include new IT technologies and platforms – Cloud, Mobile devices.
Next level of verification productivity
Where is the next level of verification productivity likely to come from? To this, Jalan replied that productivity in the verification improves from different aspects.
While faster tools with increased capacity comes from innovation at EDA end, standard have played an excellent role in addressing it. UVM has helped in displacing vendor specific technologies to improve inter-operability, quick ramp up for engineers and reusability. Similarly on power format, UPF has played an important role in bridging the gaps.
Unified coverage is another aspect where it will help in closing early with coverage driven verification. IPXACT and SystemRDL standards help further in packaging IPs and easier hand off to enable reuse. Similarly other standards on ESL, AMS etc help in closing the loop holes that prevent productivity.
New, portable stimulus specification now being developed under Accellera that will help in easing out test development at different levels from IP to sub system to SoC. For faster simulations, the increase in adoption of hardware acceleration platforms is helping verification engineers to improve regression turn around time.
Formal technologies play an important role in providing a mathematical proofs to common verification challenges at an accelerated pace in comparison to simulation. Finally events like DVCON enables users to share their experiences and knowledge encouraging others to try out solutions instead of struggling with the process of discovering or inventing one.
More Indian start-ups
Finally, do the organizers expect to see more Indian start-ups post this event? Yes, says Jalan. “We even have a special incubation booth that is encouraging young startups to come forth and exhibit at a reduced cost (only $300). We are creating a platform and soon we will see new players in all areas of Semiconductor.
“Also, the Indian government’s push in the semiconductor space will give new startups further incentive to mushroom. These conferences help entrepreneurs to talk to everyone in the community about problems, vet potential solutions and seek blessings from gurus.”
Thanks to the Enable450 newsletter, sent out by Malcolm Penn, CEO, Future Horizons, here is a piece on the Metro450 Conference 2014, held earlier this year in Israel.
Metro450 is an Israel-based consortium with the goal of helping the metrology companies advance in their fields. The consortium’s members include metrology and related companies, as well as academics who support these companies by performing basic research.
The conference was sponsored by the Israeli Chief Scientist Office, by Applied Materials Israel and by Intel. There were several goals for the conference: to provide an opportunity for industry leaders as well as academicians to meet and discuss the latest developments in the world of metrology, to present these advances to audiences which would normally not be privy to such information, and to learn more about the international effort in 450mm wafer technology.
Over 200 people attended this conference from Israeli companies and academia, as well as from Europe and the United States. Israeli companies included Applied Materials, Jordan Valley, Nova, KLA, Zeiss Israel, and others. Academic members included researchers from the leading Israeli universities, including the Technion, Tel-Aviv U. and Haifa U. European companies were represented by ENIAC, as well as large corporations such as ASML as well SME-based companies. The G450C consortium, based in Albany, N.Y. was also well represented at this conference.
Some of the highlights of the conference included scientific discussions of different metrology methods, and their adjunct requirements, such as improved rapid wafer movement, improved sampling methods and fast computing. Presentations also included an overview of the advances necessary to move the industry forward, optical CD metrology, x-ray metrology, and novel piezo-based wafer movement.
A panel discussed various broad industry trends, including the timeline of 450mm wafers, European programs and the Israeli programs. International speakers discussed the European technology model, risk mitigation of 450 through collaborations, 450 collaborative projects under ENIAC, 450mm wafer movement challenges and metrology challenges beyond 14nm.
This second annual Metro450 conference took place this January at the Technion, Israel.