Archive for the ‘32nm’ Category

WLCSP market and industrial trends

WLCSP technology and industrial roadmap. Source: Yole Developpement, France.

WLCSP technology and industrial roadmap. Source: Yole Developpement, France.

According to Yole Developpement, France, the number of devices packaged with ‘fan-in WLCSP will exceed 25 billion units in 2012, exceeding more than 2 million 300mm equivalent wafers. Yole recently held a seminar on wafer level chip scale package (WLCSP).

Yole estimates the fan-in WLCSP industry value to be over $1.9 billion in 2012. This includes wafer level services (including test) and die level services, as well as the service margin. This market value is expected to keep on growing at a 2010-2016 CAGR of 12 percent, despite decreasing prices. However it does not grow equally across all device types.

The use of fan-in WLCSP for a given application tends to be more and more standardized: it is now clear, for example, that the penetration rate of fan-in WLCSP for connectivity devices in handsets is close to 100 percent, while some players still proposed QFN or BGA solutions a couple of years ago for this same application.

The maximum die size increased recently, and it is now common place to find 36mm² fan-in WLCSP devices in smartphones and tablets. The world record is 50mm² with 309 balls. Any fan-in WLCSP device larger than 4mm in side needs to be underfilled on the PCB. According to Yole, fan-in WLCSP is a maturing technology and market. It still grows faster than the average semiconductor packaging market mainly thanks to the fast growth rates of smartphones and tablet PCs in which WLCSP considerably helps save space and costs. Read more…

Semiconductor supply chain dynamics: Future Horizons @ IEF2011

The last decade heralded a dramatic transformation in supply chain dynamics, driven by the complexity challenge of staying on the More Moore curve. On the demand side, the high cost of fabs persuaded almost all integrated device manufacturers (IDMs) to use foundries for their leading-edge wafer supply.

The ever-increasing process complexity and its negative impact on manufacturing yields forced the adoption of sophisticated foundry-specific design-for manufacturing (DFM) techniques, effectively committing new chip designs to a single foundry and process.

At the same time, the industry adopted a much more cautious lagging rather than leading demand approach to new capacity expansion, resulting in under-supply and shortages in leading-edge wafer fab capacity. To make matters worse, the traditional oxide-based planar transistor started to misbehave at the 130nm node, as manifested by low yields and higher than anticipated power dissipation, especially when the transistors were supposed to be off, with no increase in performance, heralding the introduction of new process techniques (e.g., high-k metal gates).

Even before these structural changes have been fully digested, supply chain dynamics have been further disrupted by the prospective transition to 450mm wafer processing, to extreme ultra violet (EUV) lithography, and from planar to vertical transistor design.

Transistor design
Since the start of the industry, adding more IC functionality while simultaneously decreasing power consumption and increasing switching speed—a technique fundamentally known as Moore’s Law—has been achieved by simply making the transistor structure smaller. This worked virtually faultlessly down to the 130nm node when quite unexpectedly things did not work as planned. Power went up, speed did not improve and process yields collapsed. Simple scaling no longer worked, and new IC design techniques were needed.

While every attempt was made to prolong the life of the classic planar transistor structure, out went the polysilicon/silicon dioxide gate; although this transition was far from plain sailing, in came high-k metal gates spanning 65nm-28nm nodes. Just as the high-k metal gate structure gained industry-wide consensus at 28nm, it too ran out of steam at the 22nm-16nm nodes, forcing the introduction of more complex vertical versus planar transistor design and making the IC design even more process-dependent (i.e., foundry-dependent). Dual foundry sourcing, already impractical for the majority of semiconductor firms, will only get worse as line widths continue to shrink. Read more…

Slew of EDA announcements @ DAC 2011

June 6, 2011 Comments off

The Design and Automation Conference (DAC) 2011, kicked off today in San Diego, USA, with its usual slew of announcements. Leading the pack were Magma Design Automation and Cadence Design Systems, along with Synopsys, Mentor Graphics, and several others.

Magma Design Automation Inc. announced a partnership with Fraunhofer Institute for Integrated Circuits IIS to develop process-independent Titan FlexCell models of the Institute’s analog intellectual property (IP) cores. It also announced the availability of a netlist-to-GDSII reference flow for GLOBALFOUNDRIES’ 28nm super low-power (SLP) high-k metal-gate (HKMG) technology.

Magma announced the immediate availability of the Titan Analog Design Kit for TSMC 180nm and 65nm processes, that implements Titan’s model-based design methodology with Titan FlexCells, which are modular, process- and specification-independent, reusable analog building blocks.

Magma Design Automation also launched Silicon One, an initiative to bring focus to making silicon profitable for customers by providing differentiated solutions and technologies that address business imperatives facing semiconductor makers today – time to market, product differentiation, cost, power and performance.

Silicon One’s initial focus is on five types of devices that are key to electronic products that are most prevalent today:
* Analog/mixed-signal (AMS)
* Memory
*  Processing cores
* SoCs.

Cadence Design Systems Inc. isn’t far behind either!  It announced an array of new technologies incorporated into the new TSMC Reference Flow 12.0 and AMS Reference Flow v2.0 that ensure 28nm production readiness. Cadence also announced a close collaboration with TSMC that will extend its interface IP offering.  With Imec, in Belgium, Cadence announced a new technology that delivers an automated test solution for design teams deploying 3D stacked ICs (3D-ICs).

Cadence also announced the immediate availability of verification IP (VIP) for ARM’s new AMBA 4 Coherency Extensions protocol (ACE), extending its popular VIP catalog and speeding the development of multiprocessor mobile devices. Cadence further outlined the technologies and steps required to move the industry to advanced node design, with a particular focus on 20nm and 28nm design.

Mentor Graphics announced that the Catapult C high-level synthesis tool now supports the synthesis of transaction level models (TLMs). It also announced a unified embedded software debugging platform, from pre-silicon to final product, based on the integration of the Mentor Embedded Sourcery CodeBench embedded software development tools with Mentor’s leading electronic system level (ESL), verification, and hardware emulation products. These include the Mentor Graphics Vista Virtual Prototyping product, Veloce hardware emulator, prototype target boards, and end products or any combination thereof.

Mentor Graphics announced support for 3D-IC in TSMC’s Reference Flow 12.0 (RF12). Solutions for both silicon interposer and through silicon via (TSV) stacked die configurations are now supported by the Calibre physical verification and extraction platform and the Tessent IC test solution.

ARM and Synopsys Inc. have signed an expanded multi-year agreement extending ARM’s access to Synopsys’ innovative EDA technology. ARM will also provide Synopsys with access to the ARM Cortex-A15 processor to maximize performance and energy efficiency of SoCs built by ARM’s Partners using this advanced ARM processor and Synopsys tools. Read more…

ST intros STM32L ultra-low-power Cortex‑M3 devices

March 3, 2011 Comments off

STM32L ultra-low-power Cortex‑M3 devices.

STM32L ultra-low-power Cortex‑M3 devices.

STMicroelectronics has introduced the STM32L advanced ultra-low-power Cortex-M3 based MCU platform.

Built on cutting-edge proprietary process – robustness, it is part of a wide 32-bit product portfolio. The MCU platform is based on the just-enough energy concept and has an all inclusive package applications.

STM32L 32- to 128-Kbyte products are entering full production in the second half of March 2011. It is part of the industry’s largest ARM Cortex-M 32-bit microcontroller family with six STM32 families. STMicroelectronics is developing the STM32L portfolio up to 384 Kbytes of embedded memory. The STM32L is also Continua ready for its USB peripheral driver.

STM32L’s robustness has been derived from an automotive qualified process. It is all inclusive for ultra-low-power applications, and comes with hardware integrated features and software library packages. STM32L also has a ‘just-enough energy concept’, which includes undervolting, user controlled and an innovative architecture, all of this for less than 1 µA.

ST’s ultra-low-power EnergyLite platform features ST’s 130nm ultra-low-leakage process technology. It makes use of shared technology, architecture and peripherals. The company’s ultra-low-power portfolio for 2011 will be in production second half of March 2011. Many others will also be in production in the second half of April 2011. In fact, there will be over 100 part numbers from 4- to 384-Kbyte flash, and from 20 to 144 pins.

STM32L is based on ultra-low-power architecture, which is all inclusive for ultra low power applications. It also features ultra-low voltage, with power supply down to 1.8 V with BOR and also down to 1.65 V without BOR.The analog functional can be down to 1.8 V and the reprogramming capability can be down to 1.65 V.

STM32L is also flexible and secure, featuring +/- 0.5 percent internal clock accuracy when trimmed by RTC oscillator. It has up to five clock sources and has the MSI to achieve very low power consumption at seven low frequencies.

It also feattures dynamic voltage scaling in Run mode. The voltage scaling optimizes the product efficiency. User selects a mode (voltage scaling) according to external VDD supply, DMIPS performance required and maximum power consumption. It features the energy saving mode as well, down to 171 µA/DMIPS from Flash in Run mode. Read more…

Round-up 2010: Best of semiconductors

December 31, 2010 2 comments

Right then, folks! This is my last post for 2010, on my favorite topic – semiconductors. If 2009 was one of the worst, if not, the worst year ever for semiconductors, 2010 seems to be the best year for this industry, what with the analyst community forecasting that the global semicon industry will surpass the $300 billion mark for the first time in its history!

Well, here’s a look at the good, the bad and the ugly, if available for otherwise what has been an excellent year, which is in its last hours, for semiconductors. Presenting a list of posts on semiconductors that mattered in 2010.

Top semiconductor and EDA trends to watch out for in 2010!

Delivering 10X design improvements: Dr. Walden C. Rhines, Mentor Graphics @ VLSID 2010

Future research directions in EDA: Dr. Prith Banerjee @ VLSID 2010 — This was quite an entertaining presentation!

Global semicon industry on rapid recovery curve: Dr. Wally Rhines

Indian semicon industry: Time for paradigm shift! — When will that shift actually happen?

Qualcomm, AMD head top 25 fabless IC suppliers for 2009; Taiwan firms finish strong!

TSMC leads 2009 foundry rankings; GlobalFoundries top challenger!

ISA Vision Summit 2010: Saankhya Labs, Cosmic Circuits are Indian start-ups to watch at Technovation 2010!

ISA Vision Summit 2010: Karnataka Semicon Policy 2010 unveiled; great opportunity for India to show we mean business! — So far, the Karnataka semicon policy has flattered to deceive! I’m not surprised, though!

Dongbu HiTek comes India calling! Raises hopes for foundry services!!

Indian electronics and semiconductor industries: Time to answer tough questions and find solutions — Reminds me of the popular song from U2 titled — “I still haven’t found what I’m looking for”!

What should the Indian semicon/electronics industry do now? — Seriously, easy to say, difficult to manage (ESDM)! 😉  Read more…

Is enough being done for Indian industry-academia collaboration in VLSI education?

November 20, 2010 14 comments

Do you, as a semiconductor/VLSI/EDA company, run university or educational programs for colleges and institutes? Am sure, you do!

Well, are you providing these various colleges and institutes with the latest tools and EDA software? Perhaps, yes! So, do you regularly check whether your tool is being used properly, or at all? What do you do if the tool remains unopened or unused? Okay, before all of that, are you even guiding the faculty and students to tackle real world problems associated with chip design?

Do the students (and the faculty) know the intricacies of 22nm, 32nm, 45nm, and so on? Are you able to assist students in taping out? Right, is the syllabus taught in all of these colleges good enough to produce the kind of talent and skills that the semiconductor/VLSI industry requires currently, and in the future? Is everything being taught, the latest?

As they say — it takes two to tango… and, it takes two hands to clap! To the Indian academia — how many among you are “really” serious about being trained on a regular basis by the semicon/VLSI/EDA industry? What have you all done about it so far, all of these years? How many colleges and institutes among you (and do you) regularly put up or raise your hand to the industry and say — we lack the knowledge in a particular area and need training – please help us!

The question is: what are you, as a semicon/VLSI/EDA company, doing about training the various faculty and the students in various colleges and institutions across India? Do you have a proper program in place for this activity? Well, is enough being done regarding the industry-academia collaboration in VLSI education in India? What more needs to be done?

Are you, as a college or institute teaching VLSI, happy with the quality of talent coming out? Are you really satisfied with the quality of B.Tech/M.Tech projects? Do you seek industry’s help regarding training on a regular basis? What steps do you take to reach out to them? And, what are you doing about it all? Do you take that initiative seriously?

For that matter, are there easy-to-use systems that enable effective and industry-relevant education? Are those being made use of properly? Can entry barriers be lowered for students and faculty so they can explore an IP idea that has business potential? How many of the colleges have done this? I know of some folks trying to develop such solutions, but that’s a separate story for another day!

Coming back on track, apparently, some semicon companies and few well known Indian institutes are really exceeding themselves, but the same story does not hold true everywhere. Why is it so?

There could be a variety of reasons, and not all are listed here. Is it a lack of initiative on part of the industry and the institutes? Don’t they even talk to each other? Are institutes not able to approach semicon companies and vice versa? Or, is it the locations of the institutes themselves? Is it that not all institutes are concerned about teaching their students how to solve real world chip design problems?

An industry friend had once remarked: As of the last three-four years, students from the Eastern part of India have no clear pathway that they can pursue to get into VLSI design. The reasons are — there are no training institutes in the East, which can teach Synopsys or Cadence tools or even the basics of Xilinx FPGA design.

A very interesting panel discussion titled Forging win-win industry-academia collaboration in VLSI education was held during the Cadence CDNLive India University conference.

Moderated by Dr. C.P. Ravikumar, technical director, University Relations, TI India, the panelists were Dr Ajit Kumar Panda from NIST Behrampur, K Krishna Moorthy, MD, National Semiconductor India, Dr K. Radhakrishna Rao, head, analog training, TI. India and R. Parthasarathy, MD, CADD Centre.

I have already covered Dr. Ravikumar’s remarks separately.

Let’s see what the other panelists have to say about all of this, and whether they have answers to all of the questions or problems. Well, this is another long post, so please bear with me! 😉 Read more…

AMD’s roadmap 2009 provides lots of answers… now, to deliver!

November 14, 2008 Comments off

AMD’s roadmap 2009, or guidance, presented during its 2008 Financial Analyst Day on Nov. 13th, provided a lot of answers to several of the questions it had been facing. Also, AMD did something Intel hasn’t! It did not revise the Q4 guidance!! During a webcast, AMD CFO, Bob Rivet, said he would offer an update to the company’s earnings outlook in the first week of December. Also, one of AMD’s announcements, the Yukon, is definitely not going to take on Intel’s Atom, and should be priced higher.

Kicking of proceedings, Dirk Meyer, President and CEO, talked about a complete AMD & Foundry Company realignment, which includes executing key technology transitions. These include: deliver 2nd wave of 45nm products and platforms — including chipsets; transition to 40nm graphics products; finalize 32nm designs for 2010 production. Also, deliver, market and sell platforms; and continue operational excellence.

Later, during the Q&A session, when asked about the validity of AMD’s cross-license for patents with Intel, Meyer said there was no legal issue. AMD’s agreement with Intel allows AMD subsidiaries to be licensed. The Foundry Company, 43.5 percent owned by AMD, qualifies as a subsidiary, as defined, as per the agreement with Intel.

Asset Smart strategy
According to Rivet, who spoke last during the Webcast, it has been a tough operating environment. However, AMD launched Asset Smart; achieved operating profitability in Q3-08 and is now making progress toward $1.5B operating income breakeven by early ‘09. It also has a richer MPU product mix and the first 45nm product has been launched. Graphics has returned to operating profitability. AMD has already divested its DTV business and plans to sell handheld.

Asset Smart manufacturing strategy
* Strategic commitment from Mubadala
* The Foundry Company plans multi-billion dollar build-out of leading edge fabs in Dresden and Upstate New York
* Expanded IBM partnership delivering leading-edge bulk and SOI process technology

Stronger financial structure
* ~$1B new cash investment
* ~$1.2B debt assumed by The Foundry Company
* Future fab capital expenditures optional
* Reduced process technology R&D costs
* Improved free cash flow by elimination of required fabrication capital expenditures offset somewhat by wafers purchased for cash (foundry model)
* Leaner and more variable business model, with a lower breakeven point of ~$1.5B

The Foundry Company
Doug Grose, Senior VP, Manufacturing & Supply Chain Management and Incoming CEO, The Foundry Company, highlighted AMD’s 2009 manufacturing priorities. These are: transition to best-in-class foundry model; complete conversion to 45nm production; and successful 32nm technology development.

This October 7, AMD and the Advanced Technology Investment Co. announced their intention to create a new global enterprise, The Foundry Company, to address the growing global demand for independent, leading-edge semiconductor manufacturing. This announcement was the lynchpin of AMD’s Asset Smart plan, and a key initiative designed to enable the company to achieve sustainable profitability.

At the 2008 AMD Financial Analyst Day event, AMD provided more details on what its manufacturing operations will look like once the spin-out of The Foundry Company is complete.
* For the Silicon on Insulator (SOI) and bulk manufacturing processes needed to build AMD CPUs and APUs, The Foundry Company plans to offer AMD 65nm, 45nm and 32nm manufacturing capabilities at:
– Fab 36 (Dresden)
– Fab 38 (Dresden)
– Fab 4x (Saratoga County, NY)
* For the bulk manufacturing processes AMD uses to manufacture its chipsets and GPUs, AMD plans to have access to 55nm, 40nm and 32nm manufacturing capabilities at:
– TSMC/UMC (Taiwan)
– Fab 38 (Dresden)
– Fab 4x (Saratoga County, NY)
* The Foundry Company also provided an update on its progress towards moving to a new 32nm manufacturing process for bulk and SOI production. The company confirmed that it will complete 32nm test chips in Dresden by the end of year, and is on schedule to successfully incorporate High-k Metal Gate within this process node. 32nm technology development will ramp in late 2009 in preparation for 1H 2010 volume production.

Platforms for ultraportable notebooks and mini-notebooks
There has been lot of interest in ultraportable notebooks and mini-notebooks, owing to their small form factor and lightweight profile. AMD also announced new platforms aimed at serving these markets.
* AMD introduced two ultraportable notebook platforms — Congo and Yukon. Congo is based on the dual-core Conesus CPU with the RS780M and SB710 chipset. Yukon is based on a single-core CPU with the RS690E and SB600 chipset. While targeted at the ultra-portable market, these platforms are designed to address a portion of mini-notebook market, especially at the dissatisfied users of limited Internet experience of mini-notebooks. Yukon is planned to be available in 1H09 followed by Congo in 2H09.
* AMD announced the 2010 ultraportable notebook platform code named Nile. It will feature dual-core Geneva CPU utilizing DDR3.
* In 2011, AMD plans to introduce the dual-core Ontario APU for ultraportable and mini-notebook platforms.

Server platforms
* Fiorano, the first AMD platform to combine AMD server processors and chipsets. It is on schedule for mid-2009 introduction based on planned release of the AMD SR5690 chipset. Fiorano will likely support Shanghai and the upcoming six-core Istanbul processor in 2H09.
* AMD’s next-generation, DDR3-based server platform, Maranello, remains on track for introduction in 1H10.

Desktop platforms
* Dragon is set to launch in Q1 2009 and feature AMD’s upcoming 45nm AMD Phenom II X4 quad-core processors, codenamed Deneb.
* Kodiak is scheduled to enhance AMD Business Class platforms in 2H09.
* Pisces mainstream desktop platform will debut in 2H09.
* Maui is its new home theater platform planned for launch in Q408.

There you have it! Everyone wants the global semiconductor industry to be humming and chirping! It would be great if AMD delivers on its promise and hopefully, becomes profitable all over again as well.

For those keen, PDF files of all of AMD’s presentations can be downloaded from its web site.

Intel showcases world’s first Moorestown platform at IDF Taiwan

October 24, 2008 Comments off

Intel showcased the world’s first Moorestown platform at the recently held Intel Developer Forum in Taipei, Taiwan.

In his opening keynote on Day 1 at the IDF: Innovating a New Reality, Anand Chandrasekher, Senior Vice President, General Manager, Ultra Mobility Group, Intel Corp., said: “It is a world in transformation. There have been 3 billion new entrants in the global economy. The resilience of the global economy has been incredibly strong. The Internet has equalized the level-playing field.”

He added how technology innovation and strong industry collaboration have driven the digital economy over the past 40 years, and the universal impact that the Internet and mobile Web has had in people’s lives.

“Technology innovation is the catalyst for new user experiences, industry collaborations and business models that together will shape the next 40 years,” said Chandrasekher. “As the next billion people connect to and experience the Internet, significant opportunities lie in the power of technology and the development of purpose-built devices that deliver more targeted computing needs and experiences.”

Asia’s growing might
Chandrasekher added: “IT is more important today, than it has ever been over the last 20 years. Asia has been playing a dramatic role.” In fact, in 2007, Asia accounted for over 25 percent of Intel’s revenue. “Look at the PC companies. ASUS, Acer, Lenovo, etc., are now in the top 10. The number of PCs in China exceeds the US’s population. There are more handsets in Taiwan than the people in Taiwan,” he highlighted. As for the Internet, Asia is now the fastest growing region online.

The foundation of the Internet is silicon, whose foundation is the Intel architecture (IA). Chandrasekher said: “It is the ecosystem for growth, tomorrow. If you don’t have the tools to drive the Internet ecosystem, you have fallen behind.” As a comparison, during 1971, the 4004 processor had 2,250 transistors. In 2008, the Core 2 Quad processor has 820 million transistors. It also consumes 93 percent less power. “Process is one piece of the foundation. Architecture is the other,” he added.

Welcome Nehalem!
Chandrasekher next focused on the upcoming Nehalem microarchitecture, which, he said, has an extremely energy efficient design. “We have introduced the turbo mode and dynamic power management. We have hyper-threading technology as well.” He pointed out that Intel has a 32nm version of the Nehalem, which should be out soon. “There has been a huge performance increase, almost 2X, with Nehalem.”

According to him, developers love parallel programming and the Intel IA. “We are giving the Larabee. It increases the throughput performance and the programmability.”

World’s first working Moorestown platform
The event’s showstopper: a live video from a Moorestown lab in Taiwan, which also demonstrated the world’s first working Moorestown platform! The Moorestown platform is scheduled for 2009-2010 timeframe.

Moorestown comprises of an SoC, codenamed “Lincroft,” which integrates the 45nm processor, graphics, memory controller and video encode/decode onto a single chip and an I/O hub codenamed “Langwell”, which supports a range of I/O ports to connect with wireless, storage, and display components in addition to incorporating several board level functions.

Chandrasekher showed off a ”Moorestown” wafer to the delegates.

In the next blog, I will introduce you to the Father of the Atom!

Mentor Graphics: DFM is where all the value is!

September 28, 2008 Comments off

As promised, here is the concluding part of my discussion with Joseph Sawicki, vice president & GM, Design to Silicon Division, Mentor Graphics.

We went over the design for manufacturing (DFM) challenges and how yield can be improved. He also touched upon the design challenges in 45nm and 32nm, respectively.

Given that the semiconductor industry does speak a lot about DFM, what steps are being taken to improve on the overall yield?

According to Sawicki, in the VLSI microchip era, yields started at 60-70 percent, and so DFM wasn’t required. However, in the nanochip era, DFM is where all the value is. [VLSI Research.]

Joseph Sawicki, vice president & GM, Design to Silicon Division, Mentor GraphicsHe added that at smaller geometries, manufacturing variability has a much greater impact on timing, power dissipation, and signal integrity. Traditional guardbanding is no longer sufficient to guarantee competitive performance at acceptable yields, and excessive design margins erase the advantages sought by going to the next node in the first place.

Moving to advanced technologies without dealing effectively with manufacturing variability can actually put a design at a competitive disadvantage due to low parametric yield.

“Successful IC implementation requires a detailed understanding of how variability affects both functional and parametric yield. Customers need a manufacturing-aware engineering approach that extends across the entire physical implementation life cycle, starting with cell library development and extending through place and route, physical verification, layout optimization, mask preparation, testing, and failure analysis.

“They need a design flow that helps them “co-optimize” for both performance and yield simultaneously, based on accurate models of manufacturing process variability. The ability to do this quickly and effectively can give IC designers a powerful competitive advantage,” Sawicki said.

There is no silver bullet! It takes a broad-based, well-integrated approach to have a significant and consistent impact on manufacturability.

According to him, Mentor Graphics provides a complete manufacturing-aware design-to-silicon solution addressing random particle effects, small-scale device and interconnect interactions, lithographic distortions and process window variations, and thickness variations resulting from chemical-mechanical polishing (CMP) and variable film deposition and etch rates.

“Our tools incorporate comprehensive, highly-accurate models that have been tuned and verified for specific manufacturing environments, and address every stage of the digital IC implementation life cycle,” he added.

So, how is Mentor handling 45nm and 32nm design challenges?

Sawicki added: “Advanced process nodes present challenges at every stage of IC implementation, from place-and-route, through physical verification, layout enhancement, testing and yield analysis. Mentor has a complete design-to-silicon flow that addresses the critical challenges of IC implementation at every stage.”

Top 10 global semicon predictions — where are we today

May 17, 2008 Comments off

It is always interesting to write semicon blogs! Lots of people come up to me with their own comments, insights, requests, etc. One such request came from a friend in Taiwan, who’s involved with the semiconductor industry.

I was asked forthrightly what I thought of the top 10 global predictions, which I had blogged/written about some time back late last year.

Top 10 semicon predictions
For those who came in late, here are the 10 global predictions on semiconductors made at that time (late December 2007.

1. Semiconductor firms may have to face a recession year in an election year.
2. DRAM market looks weak in 2008.
3. NAND market will remain hot.
4. Power will remain a major issue.
5. EDA has to catch up.
6. Need to solve embedded (software crisis?) dilemma.
7. Consolidation in the fab space.
8. Capital equipment guys will continue to move to other market.
9. Spend on capital equipment to drop.
10. Mini fabs in developing countries.

Well, lot of water has flowed since those predictions were made. Let’s see how things stand, as of now. The updated predictions would look something like these:

1. There have been signs of recession, but the industry has faced it well, so far. In fact, Future Horizons feels that if there is going to be a global economic recession, the chip industry (but not all companies) is in the best shape possible to weather the ensuing storm.

2. Memory market is changing slightly as well, though people are very cautious. According to Converge, memory market prices appear to be stabilizing. iSuppli has predicted a poor year for DRAM though!

3. NAND Flash could show some recovery later this year. Yes, Q1-08 QoQ sales seems to have slipped, but the market remains hopeful of a recovery. Even iSuppli warned of NAND Flash slowdown in 2008, while Apple slashed its NAND order forecast significantly for 2008! Keep those fingers crossed!!

4. Power remains a big issue, and will continue to be so. This will remain as we move up newer technology process nodes.

5. EDA is seemingly catching up with 45nm designs. Magma, Synopsys, and the other leading EDA vendors are said to be playing big roles in 45nm designs.

6. Fabless companies are gaining in strength. No doubt about it! The 2007 semicon rankings show that. Also, Qualcomm is now the leader in the top wireless semicon suppliers, displacing Texas Instruments.

7. There have been consilidations (or long term alliances) in: a) fab space b) DRAM space. In the fab space, Intel, Samsung and TSMC have combined to go with 450mm wafer fab line by 2012. And in the DRAM space, there have been new camps, such as Elpida-Qimonda, and Nanya-Micron partnering to take on Samsung. With the global semiconductor market seeing steady decline in growth rate, which would continue, look forward to more consolidations.

8. Investments in photovoltaics (PV) have eased the pressure on capital equipment makers and spend somewhat. In fact, 2007 will be remembered as the year when the PV industry emerged as a key opportunity for subsystems suppliers and provided a timely boost in sales for those companies actively addressing this market. Perhaps, here lies an opportunity for India.

9. Mini fabs — these are yet to happen; so far talks only. In India, a single silicon wafer fab has yet to start functioning, even though it has been quite a while since the semicon policy was announced. Conversely, some feel that India should focus on design, rather than go after something as mature as having wafer fabs. However, several solar fabs — from Moser Baer, Videocon, Reliance, etc., are quite likely.

10. Moving to 45nm from 32nm is posing more design challenges than thought. This is largely due to the use of new materials. Well, 45nm will herald a totally different structure — metal gate/high-k/thin FET/deep trench design, etc. It will herald a new way of system design as well.

Now, I am not a semicon expert by any long distance, and welcome comments, suggestions, improvements from you all.

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