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Great, India’s having fabs! But, is the tech choice right?

September 13, 2013 2 comments

G450C

G450C

The government of India recently approved the setting up of two semiconductor wafer fabrication facilities in the country. It is expected to provide a major boost to the Indian electronics system design and manufacturing (ESDM) ecosystem. A look at the two proposals:

Jaiprakash Associates, along with IBM (USA) and Tower Jazz (Israel). The outlay of the proposed fab is about Rs. 26,300 crore for establishing the fab facility of 40,000 wafer starts per month of 300mm size, using advanced CMOS technology. Technology nodes proposed are 90nm, 65nm and 45nm nodes in phase I, 28nm node in phase II with the option of establishing a 22nm node in phase III. The proposed location is Greater Noida.

Hindustan Semiconductor Manufacturing Corp. (HSMC) along with ST Microelectronics (France/Italy) and Silterra (Malaysia). The outlay of the proposed fab is about Rs. 25,250 crore for the fab facility of 40,000 wafer starts per month of 300mm size, using advanced CMOS technology. Technology nodes proposed are 90nm, 65nm and 45nm nodes in phase I and 45nm, 28nm and 22nm nodes in phase II. The proposed location is Prantij, near Gandhinagar, Gujarat.

Now, this is excellent news for everyone interested in the Indian semiconductor industry.

One look at the numbers above tell me – NONE OF THESE are going to be 450mm fabs! Indeed, both will be 300mm fabs! After waiting for such a long time to even get passed by the Union Cabinet, are these 300mm fabs going to be enough for India? Is the technology choice even right for the upcoming wafer fabs in India? Let’s examine!

As you can probably see, both the projects have placed 22nm right at the very last phase! That’s very interesting!

Intel just showcased its Xeon processor E5-2600 v2 product family a few days back. I distinctly remember Intel’s Narendra Bhandari showing off the 22nm wafer sometime last week during a product launch!

For discussion’s sake, let’s say, a fab in India comes up by say, early 2015. Let’s assume that Phase 1 takes a full year. Which means, Phase 2, where 22nm node would be used, shall only be touched in 2016 or even beyond! Isn’t it? Where will the rest of the global industry be by then?

You are probably aware of the Global 450 Consortium or G450C, which has Intel, IBM, Samsung, GlobalFoundries and TSMC among its members.  What is the consortium currently doing? It is a 450mm wafer and equipment development program, which is leveraging on the industry and government investments to demonstrate 450mm process capabilities at the CNSE’s Albany Nanotech Complex. CNSE, also a consortium member, is the SUNY’s College of Nanoscale Science and Engineering!

So, what does all of this tell me?

One, these upcoming fabs in India will probably produce low- to mid-range chips, and some high-end ones at a later stage. Well, two, this does raise a question or two about India’s competitive advantage in the wafer fab space!  Three, there is lot of material on 450mm fabs, and some of that is available right here, on this blog! Have the Indian semiconductor industry folks paid enough attention to all that? I really have no idea!

Four, only the newer 300mm fabs built with higher ceilings and stronger floors will be able to be upgraded to 450mm, as presented by The Information Network’s Dr. Robert Castellano at the Semicon West 2013. Five, what are the likely alternative markets for 200mm and 300mm fabs? These are said to be MEMs and TSV, LEDs and solar PV. Alright, stop!

Perhaps, these product lines will be good for India and serve well, for now, but not for long!

Slew of EDA announcements @ DAC 2011

June 6, 2011 Comments off

The Design and Automation Conference (DAC) 2011, kicked off today in San Diego, USA, with its usual slew of announcements. Leading the pack were Magma Design Automation and Cadence Design Systems, along with Synopsys, Mentor Graphics, and several others.

Magma Design Automation Inc. announced a partnership with Fraunhofer Institute for Integrated Circuits IIS to develop process-independent Titan FlexCell models of the Institute’s analog intellectual property (IP) cores. It also announced the availability of a netlist-to-GDSII reference flow for GLOBALFOUNDRIES’ 28nm super low-power (SLP) high-k metal-gate (HKMG) technology.

Magma announced the immediate availability of the Titan Analog Design Kit for TSMC 180nm and 65nm processes, that implements Titan’s model-based design methodology with Titan FlexCells, which are modular, process- and specification-independent, reusable analog building blocks.

Magma Design Automation also launched Silicon One, an initiative to bring focus to making silicon profitable for customers by providing differentiated solutions and technologies that address business imperatives facing semiconductor makers today – time to market, product differentiation, cost, power and performance.

Silicon One’s initial focus is on five types of devices that are key to electronic products that are most prevalent today:
* ASIC /ASSP
* Analog/mixed-signal (AMS)
* Memory
*  Processing cores
* SoCs.

Cadence Design Systems Inc. isn’t far behind either!  It announced an array of new technologies incorporated into the new TSMC Reference Flow 12.0 and AMS Reference Flow v2.0 that ensure 28nm production readiness. Cadence also announced a close collaboration with TSMC that will extend its interface IP offering.  With Imec, in Belgium, Cadence announced a new technology that delivers an automated test solution for design teams deploying 3D stacked ICs (3D-ICs).

Cadence also announced the immediate availability of verification IP (VIP) for ARM’s new AMBA 4 Coherency Extensions protocol (ACE), extending its popular VIP catalog and speeding the development of multiprocessor mobile devices. Cadence further outlined the technologies and steps required to move the industry to advanced node design, with a particular focus on 20nm and 28nm design.

Mentor Graphics announced that the Catapult C high-level synthesis tool now supports the synthesis of transaction level models (TLMs). It also announced a unified embedded software debugging platform, from pre-silicon to final product, based on the integration of the Mentor Embedded Sourcery CodeBench embedded software development tools with Mentor’s leading electronic system level (ESL), verification, and hardware emulation products. These include the Mentor Graphics Vista Virtual Prototyping product, Veloce hardware emulator, prototype target boards, and end products or any combination thereof.

Mentor Graphics announced support for 3D-IC in TSMC’s Reference Flow 12.0 (RF12). Solutions for both silicon interposer and through silicon via (TSV) stacked die configurations are now supported by the Calibre physical verification and extraction platform and the Tessent IC test solution.

ARM and Synopsys Inc. have signed an expanded multi-year agreement extending ARM’s access to Synopsys’ innovative EDA technology. ARM will also provide Synopsys with access to the ARM Cortex-A15 processor to maximize performance and energy efficiency of SoCs built by ARM’s Partners using this advanced ARM processor and Synopsys tools. Read more…

90pc fab investments for 300mm capacity: SEMI

August 31, 2008 Comments off

Recently, SEMI (Semiconductor Equipment and Materials International) released its World Fab Forecast report. This report mentions that projected decline in world semiconductor fab equipment spending of 20 percent is likely for 2008. However, a rebound of over 20 percent in spending is expected in 2009, driven by over 70 fab projects.

The August 2008 edition of this report lists 53 fab equipping projects and up to 21 construction projects for fabs in 2009. It is sincerely hoped that at least one of the fabs likely from the Southeast Asian region is from India!

With the help of Scott Smith Senior Manager, Public Relations, SEMI, I was able to get in touch with Christian Gregor Dieseldorff, Senior Manager of Fab Information and Analysis at SEMI, in an attempt to find out more about the decline in global fab spends, these new fabs, and how these fabs can lead a turnaround in the global semiconductor industry. Thanks Scott!

So what are the chief reasons for the decline in fab spends during 2008? According to Dieseldorff, given the weaker economic conditions globally, coupled with higher energy and commodity prices and the financial crisis, the overall outlook for semiconductor growth in 2008 is for low-single digit growth in both revenues and units. As such, device makers have responded by cutting back their capital spending and pushing out fab projects or putting them on hold.

I was keen to find out the geographic breakup of these 70 new fabs that are likely yo come up in 2009.

Dieseldorff advised that these are not 70 new fabs coming up in 2009. Rather, the numbers reflect 300mm fabs only, and is a mix of on-going and new projects for fabs equipping and fab construction projects in 2009.

For equipping 300mm fabs, SEMI expects about: Americas 8, China 5, Europe and Mideast 4, Japan 7, South Korea 11, SE Asia 3 and Taiwan 15.

For 300mm fab construction projects, SEMI expects about: Americas 3, China 2, Europe and Mideast 1, Japan 2, South Korea 3, SE Asia 2 and Taiwan 8.

What are the salient features of some of these new fabs likely to come up next year (for instance, new tech nodes)? Dieseldorff highlighted that about 90 percent of the investments are for 300mm capacity, and the amount of spending for advanced nodes, such as 65nm, is increasing.

“Also, device makers are building larger fabs, which are termed “mega fabs,” so, to potentially realize a greater return based on scales of economy,” he added.

How will these new fabs contribute to a better performance from the global semicon industry? This will be quite interesting to witness.

Dieseldorff said that over the past several years, demand for semiconductor devices has been quite strong, and so, the industry has had to bring on capacity to support this need, both in terms of needed capacity and technology. Even with the slower market growth in 2008, recent industry data shows healthy levels of fab capacity utilization, especially for the advanced technology generations and for 300mm manufacturing.

He added: “The expectation is that demand for semiconductors will strengthen once global economic conditions improve. So, the capacity addition that is coming online this year and the fab projects that are equipping and beginning construction in 2009 are necessary to meet the future demand.”

So how will all of this affect the overall memory market (e.g., 42pc increase in share for memory)? Dieseldorff shared his thought, a fact, known well to those in the semiconductor industry, that the memory market has been battered by declining average selling prices and a condition termed by some as “profitless prosperity.”

“Looking at demand forecasts specific to memory, tremendous growth is anticipated,” he forecasted.

However, the manufacturers in this device segment are battling it out for market share, and the general expectation is that consolidation will continue.

Also, joint-ventures and partnerships are becoming increasingly critical in the memory sector as manufacturers seek to leverage their existing resources to meet future technology and capacity requirements.

It would be interesting to find out why Taiwan and Korea are forecasted as likely to exceed Japan in fab spend?

According to Dieseldorff, in Korea, Samsung has been and is the key spender, and as a company, it will continue to invest so to have a dominant share in the memory sector.

He said: “In 2009, our expectation is for the DRAM manufacturers in Taiwan to boost spending after cutting back this year. We expect seven new 300 mm fab lines in Taiwan to come into production over the next two years.”

However, spending in Japan has been more measured and is likely to remain so. Toshiba, and its joint-venture partner, Sandisk are the big spenders in Japan, when it comes to new fab capacity. Other Japanese semiconductor manufacturers are more cautious and are focused more on technology spending.

Growth drivers for semiconductor industry

October 19, 2007 Comments off

Michael J. Fister, president and CEO, Cadence Design Systems Inc., who was in India for the CDNLive event, delivered a wonderful keynote at the recently held CDNLive. Here’s what he had to say!

The semiconductor industry is maturing. Since 2000, the industry’s annual growth rate has experienced extreme highs and lows.

Though the semiconductor industry’s revenue growth will be low in 2007, the good news is that growth rates are smoothing out as costly fabs demand consistent production. Wireless communications, computers, and consumer products continue to be the growth drivers for semiconductors. A couple of the semiconductor technology trends driving electronic design and product development are:

* More designs at advanced nodes — Beginning this year, 90nm designs will outnumber those at 130nm. Meanwhile, 65nm is design activity is ramping up and advanced designs are targeting 45nm.

* Growth in transistor count and logic — Not only are transistor counts increasing according to Moore’s Law, those transistors are being used to create more functions -– and therefore more complexity -– on a single chip, not just adding memory to the existing designs.

A related trend is that the amount of chip production outsourced to foundries continues to grow, with many Integrated Device Manufacturers (IDMs) moving to a ‘Fab-lite’ strategy for advanced nodes. This is happening as design is becoming a greater product differentiation than production.

Note that Fister’s reference to Fab-lite is interesting, even though lot of new investments are said to be getting into, and he himself says, “costly fabs demand consistent production.” There is another point that should not be overlooked — the one concerning Qualcomm, a fabless company, making it to the Top 10 semicon companies, for the first time.

Coming back the Cadence CEO, all of these trends create two kinds of challenges for chip design. These are: 1) manufacturability at advanced process nodes like 90nm and below, and 2) increased complexity and scale of chip design of system-on-chip (SoC).

Design solutions today must address these challenges, and increase team productivity and schedule predictability. To accomplish this, Cadence is focused on a holistic approach to the design flow. The Cadence Low-Power Solution and the Encounter Timing System are good examples of this holistic approach addressing the challenges of escalating scale and complexity.

The same holistic approach is shown in Cadence’s approach to manufacturability, which is to integrate design for manufacturability (DFM) into all aspects of the design flow, rather than just apply DFM techniques as a post-design step.

Categories: 45nm, 65nm, 90nm, Cadence, CDNLive, DFM, EDA, IDM, Michael J. Fister, SoC Tags: , ,
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