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ST intros STM32F4 series high-performance Cortex-M4 MCUs

September 18, 2013 Comments off

STMicroelectronics has introduced the STM32F4 series STM32 F4x9 and STM32F401, which are high-performance Cortex-M4 microcontrollers (MCUs).

On the growth drivers for GP MCUs, the market growth is driven by faster migration to 32 bit platform. ST has been the first to bring the ARM Cortex based solution, and now targets leadership position on 32bit MCUs. An overview of the STM32 portfolio indicates high-performance MCUs with DSP and FPU up to 608 CoreMark and up to180 MHz/225 DMIPS.

Features of the STM32F4 product lines, specifically, the STM32F429/439, include 180 MHz, 1 to 2-MB Flash and 256-KB SRAM. The low end STM32F401 has features such as 84 MHz, 128-KB to 256-KB Flash and 64-KB SRAM.

The STM32F401 provides thebest balance in performance, power consumption, integration and cost. The STM32F429/439 is providing more resources, more performance and more features. There is close pin-to-pin and software compatibility within the STM32F4
series and STM32 platform.

The STM32 F429-F439 high-performance MCUs with DSP and FPU are:
• World’s highest performance Cortex-M MCU executing from Embedded Flash, Cortex-M4 core with FPU up to 180 MHz/225 DMIPS.
• High integration thanks to ST 90nm process (same platform as F2 serie): up to 2MB Flash/256kB SRAM.
• Advanced connectivity USB OTG, Ethernet, CAN, SDRAM interface, LCD TFT controller.
• Power efficiency, thanks to ST90nm process and voltage scaling.

In terms of providing more performance, the STM32F4 provides up to 180 MHz/225 DMIPS with ART Accelerator, up to 608 CoreMark result, and ARM Cortex-M4 with floating-point unit (FPU).

The STM32F427/429 highlights include:
• 180 MHz/225 DMIPS.
• Dual bank Flash (in both 1-MB and 2-MB), 256kB SRAM.
• SDRAM Interface (up to 32-bit).
• LCD-TFT controller supporting up to SVGA (800×600).
• Better graphic with ST Chrom-ART Accelerator:
— x2 more performance vs. CPU alone
— Offloads the CPU for graphical data generation
* Raw data copy
* Pixel format conversion
* Image blending (image mixing with some transparency).
• 100 μA typ. in Stop mode.

Some real-life examples of the STM32F4 include the smart watch, where it is the main application controller or sensor hub, the smartphone, tablets and monitors, where it is the sensor hub for MEMS and optical touch, and the industrial/home automation panel, where it is the main application controller. These can also be used in Wi-Fi modules for the Internet of Things (IoT), such as appliances, door cameras, home thermostats, etc.

These offer outstanding dynamic power consumption thanks to ST 90nm process, as well as low leakage current made possible by advanced design technics and architecture (voltage scaling). ST is making a large offering of evaluation boards and Discovery kits. The STM32F4 is also offering new firmware libraries. SEGGER and ST signed an agreement around the emWin graphical stack. The solution is called STemWin.

Great, India’s having fabs! But, is the tech choice right?

September 13, 2013 2 comments

G450C

G450C

The government of India recently approved the setting up of two semiconductor wafer fabrication facilities in the country. It is expected to provide a major boost to the Indian electronics system design and manufacturing (ESDM) ecosystem. A look at the two proposals:

Jaiprakash Associates, along with IBM (USA) and Tower Jazz (Israel). The outlay of the proposed fab is about Rs. 26,300 crore for establishing the fab facility of 40,000 wafer starts per month of 300mm size, using advanced CMOS technology. Technology nodes proposed are 90nm, 65nm and 45nm nodes in phase I, 28nm node in phase II with the option of establishing a 22nm node in phase III. The proposed location is Greater Noida.

Hindustan Semiconductor Manufacturing Corp. (HSMC) along with ST Microelectronics (France/Italy) and Silterra (Malaysia). The outlay of the proposed fab is about Rs. 25,250 crore for the fab facility of 40,000 wafer starts per month of 300mm size, using advanced CMOS technology. Technology nodes proposed are 90nm, 65nm and 45nm nodes in phase I and 45nm, 28nm and 22nm nodes in phase II. The proposed location is Prantij, near Gandhinagar, Gujarat.

Now, this is excellent news for everyone interested in the Indian semiconductor industry.

One look at the numbers above tell me – NONE OF THESE are going to be 450mm fabs! Indeed, both will be 300mm fabs! After waiting for such a long time to even get passed by the Union Cabinet, are these 300mm fabs going to be enough for India? Is the technology choice even right for the upcoming wafer fabs in India? Let’s examine!

As you can probably see, both the projects have placed 22nm right at the very last phase! That’s very interesting!

Intel just showcased its Xeon processor E5-2600 v2 product family a few days back. I distinctly remember Intel’s Narendra Bhandari showing off the 22nm wafer sometime last week during a product launch!

For discussion’s sake, let’s say, a fab in India comes up by say, early 2015. Let’s assume that Phase 1 takes a full year. Which means, Phase 2, where 22nm node would be used, shall only be touched in 2016 or even beyond! Isn’t it? Where will the rest of the global industry be by then?

You are probably aware of the Global 450 Consortium or G450C, which has Intel, IBM, Samsung, GlobalFoundries and TSMC among its members.  What is the consortium currently doing? It is a 450mm wafer and equipment development program, which is leveraging on the industry and government investments to demonstrate 450mm process capabilities at the CNSE’s Albany Nanotech Complex. CNSE, also a consortium member, is the SUNY’s College of Nanoscale Science and Engineering!

So, what does all of this tell me?

One, these upcoming fabs in India will probably produce low- to mid-range chips, and some high-end ones at a later stage. Well, two, this does raise a question or two about India’s competitive advantage in the wafer fab space!  Three, there is lot of material on 450mm fabs, and some of that is available right here, on this blog! Have the Indian semiconductor industry folks paid enough attention to all that? I really have no idea!

Four, only the newer 300mm fabs built with higher ceilings and stronger floors will be able to be upgraded to 450mm, as presented by The Information Network’s Dr. Robert Castellano at the Semicon West 2013. Five, what are the likely alternative markets for 200mm and 300mm fabs? These are said to be MEMs and TSV, LEDs and solar PV. Alright, stop!

Perhaps, these product lines will be good for India and serve well, for now, but not for long!

ST/Freescale intro 32-bit MCUs for safety critical applications

October 15, 2009 Comments off

Early this month, STMicroelectronics and Freescale Semiconductor introduced a new dual-core microcontroller (MCU) family aimed at functional safety applications for car electronics.

These 32-bit devices help engineers address the challenge of applying sophisticated safety concepts to comply with current and future safety standards. The dual-core MCU family also includes features that help engineers focus on application design and simplify the challenges of safety concept development and certification.

Based on the industry-leading 32-bit Power Architecture technology, the dual-core MCU family, part-numbered SPC56EL at ST and MPC564xL at Freescale, is ideal for a wide range of automotive safety applications including electric power steering for improved vehicle efficiency, active suspension for improved dynamics and ride performance, anti-lock braking systems and radar for adaptive cruise control.

Freescale/STMicroelectronics JDP
The Freescale/STMicroelectronics joint development program (JDP) is headquartered in Munich, Germany, and jointly managed by ST and Freescale.

The JDP is accelerating innovation and development of products for the automotive market. The JDP is developing 32-bit Power Architecture MCUs manufactured on 90nm technology for an array of automotive applications: a) powertrain, b) body, c) chassis and safety, and d) instrument cluster.

STMicroelectronics’ SK Yue, said: “We are developing 32-bit MCUs based on 90nm Power Architecture technology. One unique feature — it allows customer to use dual core or single core operation. The objective of this MCU is to help customers simplify design and to also reduce the overall system cost.

On the JDP, he added: “We will have more products coming out over a period of time. This JDP is targeted toward automotive products.”

Commenting on the automotive market today, he said that from June onward, the industry has been witnessing a gradual sign of recovery coming in the automotive market.

1 MB safety and chassis controller -- 32-bit MCU courtesy Freescale/STMicroelectronics joint development program (JDP)

1 MB safety and chassis controller -- 32-bit MCU courtesy Freescale/STMicroelectronics joint development program (JDP)

Automotive market challenges

There has been an increasing integration and system complexity. These include:

* Increasing electrification of the vehicle (replacing traditional mechanical systems).

* Mounting costs pressure leading to integration of more functionality in a single ECU.

* Subsequent increase in use of high-performance sensor systems has driven increased MCU performance needs.

There are also increasing safety expectations. Automotive system manufacturers need to guarantee the IEC61508 (SIL3) and ISO26262 (ASILD) system-safety capability. Also, a move from passive to active safety is increasing the number of safety functions distributed in many ECUs.

Finally, there is a continued demand for quality — in form of zero defects, by which, a 10x quality improvement is expected.

MCU family addresses market challenges

The MCU family offers exceptional integration and performance. These include: high-end 32-bit dual-issue Power Architecture cores, combined with comprehensive peripheral set in 90nm non-volatile-memory technology. It also provides a cost effective solution by reducing board size, chip count and logistics/support costs.

It also solves functional safety. The Functional Safety architecture has been specifically designed to support IEC61508 (SIL3) and ISO26262 (ASILD) safety standards. The architecture provides redundancy checking of all computational elements to help endure the operation of safety related tasks. The unique, dual mode of operation allows customers to choose how best to address their safety requirements without compromising on performance.

The MCU also offers best-in-class quality. It is design for quality, aiming for zero defects. The test and manufacture have been aligned to lifetime warranty needs.

The MCU family addresses the challenges of applying sophisticated safety concepts to meet future safety standards. Yue added, “There are two safety standards — we are following those guidelines.” These are the IEC61508 (SIL3) and ISO26262 (ASILD) system-safety capabilities.

The automotive industry is also targeting for zero defects. “Therefore, all suppliers in tier 1 and 2 need to come up with stringent manuyfaturing and testing process that ensures zero defects,” he said.

32-bit dual-issue, dual-core MCU family

Finally, why dual core? Yue said that the MCU helps customers to achieve to achieve safety and motor control. Hence, dual core will definitely help deliver results.

“In many automotive applications, especially in safety-related applications, we want to have redundancy for safety. In the lock-step mode, two cores run the same task simultaneously, and results are then compared to each other in every computation. If the results are not matched, it indicates that there are some problems.”

This MCU family definitely simplifies design. It uses a flexible, configurable architecture that addresses both lock-step and dual parallel operation modes on a single dual-core chip. Next, it complies with safety standards.

A redundant architecture provides a compelling solution for real-time applications that require compliance with the IEC61508 SIL3 and ISO26262 ASIL-D safety standards. It also lowers the systems cost.

Dual-core architecture reduces the need for component duplication at the system level, and lowers overall system costs.

Growth drivers for semiconductor industry

October 19, 2007 Comments off

Michael J. Fister, president and CEO, Cadence Design Systems Inc., who was in India for the CDNLive event, delivered a wonderful keynote at the recently held CDNLive. Here’s what he had to say!

The semiconductor industry is maturing. Since 2000, the industry’s annual growth rate has experienced extreme highs and lows.

Though the semiconductor industry’s revenue growth will be low in 2007, the good news is that growth rates are smoothing out as costly fabs demand consistent production. Wireless communications, computers, and consumer products continue to be the growth drivers for semiconductors. A couple of the semiconductor technology trends driving electronic design and product development are:

* More designs at advanced nodes — Beginning this year, 90nm designs will outnumber those at 130nm. Meanwhile, 65nm is design activity is ramping up and advanced designs are targeting 45nm.

* Growth in transistor count and logic — Not only are transistor counts increasing according to Moore’s Law, those transistors are being used to create more functions -– and therefore more complexity -– on a single chip, not just adding memory to the existing designs.

A related trend is that the amount of chip production outsourced to foundries continues to grow, with many Integrated Device Manufacturers (IDMs) moving to a ‘Fab-lite’ strategy for advanced nodes. This is happening as design is becoming a greater product differentiation than production.

Note that Fister’s reference to Fab-lite is interesting, even though lot of new investments are said to be getting into, and he himself says, “costly fabs demand consistent production.” There is another point that should not be overlooked — the one concerning Qualcomm, a fabless company, making it to the Top 10 semicon companies, for the first time.

Coming back the Cadence CEO, all of these trends create two kinds of challenges for chip design. These are: 1) manufacturability at advanced process nodes like 90nm and below, and 2) increased complexity and scale of chip design of system-on-chip (SoC).

Design solutions today must address these challenges, and increase team productivity and schedule predictability. To accomplish this, Cadence is focused on a holistic approach to the design flow. The Cadence Low-Power Solution and the Encounter Timing System are good examples of this holistic approach addressing the challenges of escalating scale and complexity.

The same holistic approach is shown in Cadence’s approach to manufacturability, which is to integrate design for manufacturability (DFM) into all aspects of the design flow, rather than just apply DFM techniques as a post-design step.

Categories: 45nm, 65nm, 90nm, Cadence, CDNLive, DFM, EDA, IDM, Michael J. Fister, SoC Tags: , ,
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