According to Dr. Walden C. Rhines, chairman and CEO, Mentor Graphics Corp., verification has to improve and change every year just to keep up with the rapidly changing semiconductor technology. Fortunately, the innovations are running ahead of the technology and there are no fundamental reasons why we cannot adequately verify the most complex chips and systems of the future. He was speaking at the recently held DVCON 2014 in Bangalore, India.
A design engineer’s project time for doing design has reduced by 15 percent from 2007-2014, while the engineer’s time for doing verification had seen 17 percent increase during the same time. At this rate, in about 40 years, all of a designer’s time will be devoted to verification. At the current rate, there is almost no chance of getting a single-gate design correct on first pass!
Looking at a crossover of verification engineers vs. designer engineers, there is a CAGR designers of 4.55 percent, and for CAGR verifiers, it is 12.62 percent.
The on-time completion remains constant, as we look at the non-FPGA project’s schedule completion trends, which are: 67 percent behind schedule for 2007, 66 percent behind schedule for 2010, 67 percent behind schedule for 2012, and 59 percent behind schedule for 2014. There has been an increase in the average number of embedded processors per design size, moving from 1.12 to 4.05.
Looking at the macro trends, there has been standardization of verification languages. SystemVerilog is the only verification language growing. Now, interestingly, India leads the world in SystemVerilog adoption. It is also remarkable that the industry converged on IEEE 1800. SystemVerilog is now mainstream.
There has been standardization in base class libraries as well. There was 56 percent UVM growth between 2012 and 2014, and 13 percent is projected growth in UVM the next year. Again, India leads the world in UVM adoption.
The second macro trend is standardization of the SoC verification flow. It is emerging from ad hoc approaches to systematic processes. The verification paradox is: a good verification process lets you get the most out of best-in-class verification tools.
The goal of unit-level checking is to verify that the functionality is correct for each IP, while achieving high coverage. Use of advanced verification techniques has also increased from 2007 to 2014.
Next, the goal of connectivity checking is to ensure that the IP blocks are connected correctly, a common goal with IP integration and data path checking.
The goal of system-level checking is performance, power analysis and SoC functionality. Also, there are SoC ‘features’ that need to be verified.
A third macro trend is the coverage and power across all aspects of verification. The Unified Coverage Interoperability Standard or UCIS standard was announced at DAC 2012 by Accellera. Standards accelerate the EDA innovation!
The fourth trend is active power management. Now, low-power design requires multiple verification approaches. Trends in power management verification include things like Hypervisor/OS control of power management, application-level power management, operation in each system power state, interactions between power domains, hardware power control sequence generation, transitions between system power states, power domain state reset/restoration, and power domain power down/power up.
Macro enablers in verification
Looking at the macro enablers in verification, there is the intelligent test bench, multi-engine verification platforms, and application-specific formal. The intelligent test bench technology accelerates coverage closure. It has also seen the emergence of intelligent software driven verification.
Embedded software headcount surges with every node. Clock speed scaling slows the simulation performance improvement. Growing at over 30 percent CAGR from 2010-14, emulation is the fastest growing segment of EDA.
As for system-level checking, as the design sizes increase emulation up, the FPGA prototyping goes down. The modern emulation performance nmakes virtual debug fast. Virtual stimulus makes emulator a server, and moves the emulator from the lab to the datacenter, thereby delivering more productivity, flexibility, and reliability. Effective 100MHz embedded software debug makes virtual prototype behave like real silicon. Now, integrated simulation/emulation/software verification environments have emerged.
Lastly, for application-specific formal, the larger designs use more formal. The application-specific formal includes checking clock domain crossings.
A few weeks ago, I was fortunate enough to be able to speak with Dr. Pradip Dutta Corporate Vice President and Managing Director, and Treasurer, regarding the state of the global EDA industry and in India. What followed was a very interesting conversation, some of which is reproduced here!
Any sign of improvements in EDA?
To start with, the state of the global EDA industry is well known, and it has also seen revenue drops Q-on-Q in the past. Are there any signs of improvement?
According to Dr. Dutta, the last several quarters in the semiconductor industry have been extremely challenging as consumer demand for electronic products has declined with the heavy stress on the global economy.
“While we are starting to see signs of the semiconductor industry rebounding off the bottom with inventory replenishment and an uptick in end demand for key consumer items such as PCs and mobile phones, the environment is expected to remain difficult at least well into next year.
“During this time, the challenge for the semiconductor industry and its suppliers will be to find the next level of efficiency. The good news is that across a broad field of applications, semiconductors are a key enabler to future prosperity. Green solutions, low-cost netbooks, advances in connectivity and evolving products like the Kindle are just a few examples of areas that could help drive future development.
“The long-term ramifications of this scenario on the EDA industry are starting to become visible. More than ever, customers want to get their products out on time, and get it right with high quality.
“In addition to some immediate cost-cutting to respond to the crisis, most semiconductor and design businesses are re-focusing their market strategies, streamlining their operations, de-risking their supplier and partner relationships, and in some cases actively pursuing consolidation opportunities to drive economic efficiency.
“This situation presents as an opportunity for EDA companies to focus on important product developments that can enable leading semiconductor design and manufacturing companies to not only create more advanced devices, but to simultaneously lower risks and cut costs. In today’s economy, companies need to find ways to manage expenses while still investing in the future so they don’t just survive the recession, they emerge from it stronger.”
State of the Indian EDA industry
Obviously, it would be interesting to see how is the Indian EDA industry holding up in these times.
Dr. Dutta said that the Indian EDA industry is a combination of catering to global semiconductor players and addressing the needs of a domestic market that is slowly developing. The global players that operate out of India are rapidly moving up the value chain in terms of owning and architecting the next generation chips. This leads to an enormous opportunity for EDA companies to get associated at the front end of tool decisions.
“As you are aware, the level of technology that is being witnessed in the chips that are getting designed here is absolutely bleeding edge. The EDA companies are therefore paying concomitant attention to robust application support and in-house R&D effort. It has to be a full package here and now to address these kinds of customer requirements.
“Beyond the global players, India is seeing a few, but committed fabless design companies coming up in recent times. In addition to that, the Indian government is showing a lot of interest in country-specific programs, primarily in defense areas that require EDA support.
“We have also recently seen media reports about an “India Chip” being conceived at the central government level for domestic security applications. The ISA is working toward a blueprint for targeting semiconductors into a national agenda and hopefully, many ideas for systems and corresponding chips that will emanate from it to keep EDA companies interested,” he added.