Archive for the ‘chip designers’ Category

Analog Devices launches portable lab for electronic circuit design

Analog Devices, as part of its University Program, has launched a personal, affordable and portable lab for electronic circuit design in India at the 26th international conference on VLSI, currently ongoing in Pune, India.

Somshubhro Pal Choudhury, MD, Analog Devices India Pvt Ltd said that miniaturization and portability are the key trends today. Desktops have given way to laptops, and then to smartphones and tablets. The expensive vital signs monitoring equipment in hospitals is giving way to more wearable miniaturized power sipping (and not guzzling) medical gadgets. It is natural that education and training for engineering students start taking a similar route.

What is this personal lab?
What it means that the lab will fit in the palm of your hand and would enable students to learn analog and mixed signal design, anywhere and everywhere not limited by their expensive university/college lab setup where access is fairly limited and the amount of time is limited as well to a few hours every week.

Analog Devices' portable lab.

Analog Devices’ portable lab.

What does it mean for students?
With the lab, now, the students can carry on their experiments in their hostels/dorms and in their classrooms, using this portable lab, run experiments quickly during the class to see how real time real-life how a certain change in circuit impacts the results.

It has all the elements of a complete and expensive Lab setup on this portable kit connected with the student’s laptop. Students would not need equipment like oscilloscopes, waveform generators, logic analyzers and power supplies, expensive equipment that only top universities can afford.

Along with the portable kit, online and downloadable software and teaching materials, circuit simulation tools, online support and community, online textbook, reference designs and lab projects to design to enhance learning as a supplement to their core engineering curriculum are also provided free of charge.

This launch is likely to revolutionize electronic circuit design education and learning among the engineering academic community.

Is enough being done for Indian industry-academia collaboration in VLSI education?

November 20, 2010 14 comments

Do you, as a semiconductor/VLSI/EDA company, run university or educational programs for colleges and institutes? Am sure, you do!

Well, are you providing these various colleges and institutes with the latest tools and EDA software? Perhaps, yes! So, do you regularly check whether your tool is being used properly, or at all? What do you do if the tool remains unopened or unused? Okay, before all of that, are you even guiding the faculty and students to tackle real world problems associated with chip design?

Do the students (and the faculty) know the intricacies of 22nm, 32nm, 45nm, and so on? Are you able to assist students in taping out? Right, is the syllabus taught in all of these colleges good enough to produce the kind of talent and skills that the semiconductor/VLSI industry requires currently, and in the future? Is everything being taught, the latest?

As they say — it takes two to tango… and, it takes two hands to clap! To the Indian academia — how many among you are “really” serious about being trained on a regular basis by the semicon/VLSI/EDA industry? What have you all done about it so far, all of these years? How many colleges and institutes among you (and do you) regularly put up or raise your hand to the industry and say — we lack the knowledge in a particular area and need training – please help us!

The question is: what are you, as a semicon/VLSI/EDA company, doing about training the various faculty and the students in various colleges and institutions across India? Do you have a proper program in place for this activity? Well, is enough being done regarding the industry-academia collaboration in VLSI education in India? What more needs to be done?

Are you, as a college or institute teaching VLSI, happy with the quality of talent coming out? Are you really satisfied with the quality of B.Tech/M.Tech projects? Do you seek industry’s help regarding training on a regular basis? What steps do you take to reach out to them? And, what are you doing about it all? Do you take that initiative seriously?

For that matter, are there easy-to-use systems that enable effective and industry-relevant education? Are those being made use of properly? Can entry barriers be lowered for students and faculty so they can explore an IP idea that has business potential? How many of the colleges have done this? I know of some folks trying to develop such solutions, but that’s a separate story for another day!

Coming back on track, apparently, some semicon companies and few well known Indian institutes are really exceeding themselves, but the same story does not hold true everywhere. Why is it so?

There could be a variety of reasons, and not all are listed here. Is it a lack of initiative on part of the industry and the institutes? Don’t they even talk to each other? Are institutes not able to approach semicon companies and vice versa? Or, is it the locations of the institutes themselves? Is it that not all institutes are concerned about teaching their students how to solve real world chip design problems?

An industry friend had once remarked: As of the last three-four years, students from the Eastern part of India have no clear pathway that they can pursue to get into VLSI design. The reasons are — there are no training institutes in the East, which can teach Synopsys or Cadence tools or even the basics of Xilinx FPGA design.

A very interesting panel discussion titled Forging win-win industry-academia collaboration in VLSI education was held during the Cadence CDNLive India University conference.

Moderated by Dr. C.P. Ravikumar, technical director, University Relations, TI India, the panelists were Dr Ajit Kumar Panda from NIST Behrampur, K Krishna Moorthy, MD, National Semiconductor India, Dr K. Radhakrishna Rao, head, analog training, TI. India and R. Parthasarathy, MD, CADD Centre.

I have already covered Dr. Ravikumar’s remarks separately.

Let’s see what the other panelists have to say about all of this, and whether they have answers to all of the questions or problems. Well, this is another long post, so please bear with me! 😉 Read more…

Cadence VLSI certification program (CVCP) aims to deliver ‘industry grade’ graduates

November 19, 2010 37 comments

Cadence Design Systems presented a curtain raiser on the Cadence VLSI Certification Program (CVCP) during the CDNLive India University conference. The availability of trained manpower holds the key to sustained growth. Also, the first thing required to build a good product is to have a good design. Hence, the need for good chip designers.

Cadence already has over 300 program participant institutes in India. The company regularly conducts ‘train the trainer’  programs as well. This program has so far witnessed the tapeouts of five chips and includes IPs from 14 colleges.

Cadence has also started additional strategic programs. First, finishing schools — initiatives with some universities and Indian semiconductor houses. These have been established to bridge the skill gap. Cadence has seen some success in Hyderabad and Bangalore. It has also contributed to the industry demand of manpower. Cadence also has the Orcad training program.

Joint development activity has been happening within the industry-academia to provide a consistent quality of curriculum and develop broader penetration.

The enablers/catalysts are industry veterans, who accept their social responsibility of training upcoming engineers. Some of the first movers aer already Cadence’s training partners.

CVCP initiative
Cadence’s CVCP has been launched with objective of delivering graduates that are ‘industry grade’. It will also provide an incremental training approach, leading up from VLSI fundamentals to industry relevant skills.

The industry relevant leading edge course work has been developed and proven through various programs such as the Cadence-Brazil initiative. Graduates will undergo hands-on guided development projects. The CVCP’s duration is of 214 hours spread over six months. It offers the following:
* MTEch in VLSI.
* MTech in digital electronics.
* MTech in embedded systems.
* BE/BTech in ECE, EE, TC.

The course will be running concurrent to the ongoing degree. Cadence owns the course, which is delivered by CCTP with support from CDNS. NIST, Berhampur, in Orissa, is the first participant in the CVCP with a batch of 60 students.

Synopsys on Discovery 2009, VCS2009 and CustomSIM

April 8, 2009 Comments off

If you’ve been following the EDA industry closely, you’d be well aware of three major announcements by Synopsys over the last couple of days. These are:

* Synopsys introduced the Discovery 2009 verification platform, delivering faster, unified verification solutions.
* It unveiled the VCS multicore technology, delivering 2x verification speed-up.
* It introduced the CustomSim Unified Circuit Simulation solution, which addresses custom digital, analog and memory verification challenges.

I met up with Dr. Pradip K. Dutta, Corporate Vice President & Managing Director, Synopsys (India) Pvt Ltd and Manoj Gandhi, vice president and general manager, verification group @ Synopsys, in an attempt to understand how significant these announcements are for verification.

Verification is huge!
According to Manoj Gandhi, at the macro level, design complexities continue to grow. As this grows, one big challenge is verification. The reason is: today’s SoC designs and large IC designs, they are being approached like large software projects.

He said: “Verification becomes huge, like software. It is expensive in hardware design. We focus on the verification challenges. We introduced the System Verilog about four to five years ago, and we had also acquired ArchPro. Yesterday, we announced the Discovery 2009, CustomSim and VCS2009.”

How can users make use of new CPUs coming out? “We aim to get higher much performance using multicore architecture,” he added.

Introducing VCS2009
The VCS2009 is multicore enabled, runs the industry’s first low-power verification methodology, and enables fastest mixed-signal simulation with the CustomSIM. Focusing on the VCS2009, Gandhi said: “In verification, there’s a design under test and verification. A lot of designs now have multicores. AMD is among the many folks using the VCS2009. Almost every CPU is designed using VCS. It plays a big role in large SoCs.”

Design companies have several activities such as test bench, debug, etc. All of these can now be parallelized. “Customer designs can be simulated on multiple threads,” Gandhi said. “Also, the applications can also be simulated on different threads, called application level parallelism. We can actually bring about 5-7X improvement in verification with the VCS2009.”

According to him, this product is already being used by some large customers. “This is our next phase of performance innovation. The processor roadmap is getting more and more multicore. We have over 200 customers,” he added.

The VCS distributes time consuming activities across multiple cores. Gandhi added that each core has a lot of computations. You may do lot of parallel activities with the mobile phones. All activities are now in parallel.

And how about the speed-up from parallel computation with the industry-leading Native Testbench (NTB)? He said: “We were one of the first to introduce all technologies as part of a single compiler. That brought the 5X speed-up. We did all of this in verification, and a test bench core was brought into verification.”

The combination of DLP and ALP optimizes VCS performance over multicore CPUs. Design level parallelism (DLP) and application level parallelism (ALP) — all CPUs can be threaded on different cores.

Low-power verification methodology published
Synopsys has published a book on industry’s first low-power verification methodology, along with ARM and Renasas. It is an attempt to bring technology to the mainstream — how to do low-power verification. There are other 30 companies who participated in this exercise.

On the CPF vs. UPF debate, he said that UPF is a standard where Magma, Mentor, Synopsys, etc. have participated. Cadence has CPF. Users can make use of this book and apply, on top of both UPF and CPF.

Introducing Discovery 2009
According to Synopsys, this solution is doing very well in the market. The company has seen strong technology leadership over the last two to three years. It has also created strong investments.

CustomSIM is a unified circuit simulation solution. “We have a software to silicon verification focus. We are all the way from system level design to RTL, to software verification, etc. Discovery has some technologies as part of that, noted Gandhi.

What has Synopsys done right?
A most interesting point in the EDA industry, I feel, has been the performance of Synopsys, in an otherwise difficult segment over the past year. So, what are the reasons behind this success?

Gandhi added: “Our management are all strong technologists. We have invested tremendously in bringing in strong technology leaders. In India, many companies needed R&D collaborations locally. For us, it was a big win when we invested in Bangalore. We work closely with customers delivering technologies that will address challenges two-three years from now.

Dr. Pradip Dutta elaborated: “Synopsys is very strong in product leadership (PL). The other two key areas are customer intimacy (CI) and operational excellence (OE). You need to be highest in PL. We have been very conservative even during strong times.”

That is indeed a marvellous thought! Those who are typically strong in technology, generally go on to develop great intimacy with customers, and all of this starts reflecting on their operations, which are anyway excellent! Here’s a message for those who wish to do well in tough times — strong product leadership, coupled with customer intimacy and well, corresponding operational excellence!

Focus on verification
Now that the focus is quite clearly on verification, how do EVE and the other verification companies stand out? EVE is currently in the emulation space. Gandhi added that EVE competes more wtih Cadence and Mentor. “We work with EVE on many accounts. Verification is all about finding bugs. Emulation has been more cyclical.”

According to him, Synopsys is now looking at tackling the next level — how do you reduce the overall cost? “We will go beyond selling tools. We would look at how to identify issues and saving verification costs.” I believe, verification takes up close to 70 percent of an overall design test.

Commenting on the EDA industry in India, both, Dr. Dutta and Gandhi feel it is still buzzing quite well, despite what’s been happening in the global context. “We have invested quite a lot. We have a large team here. We continue to collaborate with local institutions here as well,” Dr. Dutta added.

Semicon job cuts galore, but at what cost?

November 7, 2008 Comments off

The world is plagued with so many job cuts all over again, thanks to the global financial crisis! Those laid off must be getting fed up! Those who are so far lucky to survive, will be spending anxious days. Everytime we have a recession, the first thing companies do is cut jobs on the pretext of cost cutting! The semiconductor industry is also going through such an exercise at the moment!

There have been reports in the media that EDA major, Cadence, will be cutting 625 jobs! Cadence plans to achieve an annual operating expense savings of at least $150 million through a combination of workforce and other expense reductions!

AMD also announced that it will cut 500 jobs worldwide! If that’s not enough, ST-NXP Wireless, to rationalize its product portfolio and development efforts, announced a plan to reduce its global workforce by about 500, including subcontractors, from the current total of over 7500 people.

Oh my!! I wonder who all are getting laid off! I hope only very few good chip designers as possible are laid off. Otherwise, how are these companies going to maintain their momentum in the global semiconductor industry if they lay off several designers?

One question! Why do companies need to hire so many people, only to dump them at the first sign of recession? And, at what cost? Is it going to make the companies nimbler, really improve profitability, improve their market standing, etc.? I wonder!

And what of the global semiconductor industry itself? What about the so-called consolidations? Besides cost cutting, what are the industry pundits really doing to try and revive semiconductors?

We do hear a lot about poor memory market, lower capex on fabs, but well, didn’t they all see it coming?

iSuppli reported recently that mainly due to oversupply, a number of semiconductor companies have been struggling with their average selling prices (ASPs) so low that they were not profitable even before the current economic turmoil!

Further, companies may even face problems in getting credit or worse, finding investors for a next upgrade or expansion. And how do companies basically deal with problems? By cutting costs, such as laying off personnel or merging with other company which creates redundancy, leading to the same result.

Every single person laid off is a consumer, besides being the company’s valuable asset, right? If he or she wasn’t valuable enough, then why was the hiring done in the first place? Also, if he or she gets laid off, won’t that effect the economy? If yes, won’t that translate into the global economy taking a longer time to recover? Job cuts are fine, but at what cost? Is the industry thinking about all of these?

We all talk about how companies should try and must try to bring the cheer back in Christmas spending! As a friend remarked yesterday in jest — “Which Christmas? This year, or next?”

Will job cuts bring the cheer back, especially in the Christmas spends? If no, then how is it helping the semicon and electronics (and all other) industries? Can you tell me?

TI Beagle Board for Indian open source developers and hobbyists

October 18, 2008 Comments off

Texas Instruments recently introduced the pocket-size, USB-powered Beagle Board based on TI’s OMAP3530 applications processor. It features an ARM Cortex-A8 core, 2D/3D graphics engine and high-performance TMS320C64x+ digital signal processor (DSP) core.

This will help open source developers and hobbyists in India to realize their creative design ideas without being restricted by expensive hardware development tools, lackluster performance capabilities, high power consumption or stifled design environments, according to Khasim Syed Mohammed, Lead Developer for Open Platforms, Texas Instruments India Pvt. Ltd.

He added: “It helps us in learning cutting edge technology, innovating new ideas and executing them. Beagle board should be used to explore the growing demand in areas like medical, security, infotainment, navigation, education, signal processing, mobile devices and communication.”

Important for India
This initiative is particularly important in India where students can use the board to learn, show case their efforts and global recognition for their innovations.

Innovators in India should use this opportunity to prototype their ideas using the specification software hardware openly available in a never before package. It is important for the student community to learn new technologies, explore new areas and innovate. This initiative by TI also helps startups in India who want to explore the OMAP hardware but have limited support base for their requirements.

Passionate open source developers and hobbyists in India can realize their creative design ideas without being restricted by expensive hardware development tools, lackluster performance capabilities, high power consumption or stifled design environments.

Open platform innovators have the expandability of desktop machines without the expense, bulk or noise with the Beagle board, which is a powerful, low-cost and fan-less embedded system development board smaller than the size of an index card.

Board named after Beagle
The board is named after a popular breed of dogs, Beagle. It has been designed it to be one of the shortest pocket sized OMAP3530 boards. TI is encouraging the Open community to treat this as a pet, which is easy to carry and can be USB powered so that development is made easy and can perform high end applications at very less power.

Inspired to create a small, open source development board, a small group of enthusiastic engineers worked together on the concept and realization of the Beagle board. The resulting 3×3-inch board bridges desktop and embedded development by allowing developers to use the same peripherals and usage mode for almost limitless expansion. Developers are able to design exactly according to their specifications and collaborate with the community on creative new applications.

Mohammed said: “There is a growing need for development support in the Open Community. The Open Community is capable and passionate to work on industry’s high end processors and architectures and build innovative applications and prototypes for mobile, portable infotainment, portable navigation, medical, home security and many such applications. Another important reason for this initiative was the cost implications in owning a high end platform which was restricting them in exploring many such ideas/applications.”

Beagleboard is a global initiative to address the growing needs of the Open community to help them innovate and explore new areas by providing them access to leading hardware and software, giving them a forum to present their views and thoughts, showcasing their efforts for global appreciation, maintain community’s contribution.

Developers can quickly maximize their design concepts by tapping into the expertise and support of some of the industry’s top Linux programmers already experimenting with the Beagle board. With communities hosting the latest updates and codes, live forums and chats for easy collaboration, developers have easy access to support and exchange of ideas. Users are encouraged to join active, existing communities already participating in the project.

Apple shocks industry with PA Semi buy!

April 24, 2008 Comments off

According to The Unofficial Apple Web Blog (TUAW), Apple has stunned the industry by acquiring P.A. Semi, a Santa Clara based chip company founded by Dan Dobberpuhl, the former lead designer of the DEC Alpha and StrongARM processors, for US $278 million.

The Computerworld Blog reported that Apple had ‘shocked’ everyone with this move. P.A. Semi is a fabless chip designer that specializes in super low power PowerPC processors.

This move surely raises questions about Apple’s future association with Intel, which has been courting Apple since long to adopt its Atom low-power processor family. It also remains to be seen whether Apple will use these super low power PowerPC processors in embedded devices, such as high end iPhones, iPods, etc.

Interestingly, the PA Semi Web site is displaying a message: This account has surpassed its bandwidth allocation at the present time. You may reach the account administrator. Maybe, too many folks are trying to access the site to find out more about this company.

The Apple buyout of PA Semi was possibly first reported by Forbes. Since then a whole lot of articles have appeared on the Web.

According to the site, Apple spokesman Steve Dowling reportedly said, “Apple buys smaller technology companies from time to time, and we generally do not comment on our purposes and plans.” He is also said to have declined to comment on the value of the deal, which a person familiar with the deal suggested was done for $278 million in cash.

Apple later announced its quarterly earnings Wednesday. As per Apple’s financial results for fiscal 2008 second quarter ended March 29, 2008, the company posted $7.51 billion revenue and net quarterly profit of $1.05 billion, or $1.16 per diluted share.

These results compare to revenue of $5.26 billion and net quarterly profit of $770 million, or $.87 per diluted share, in the year-ago quarter. Gross margin was 32.9 percent, down from 35.1 percent in the year-ago quarter. International sales accounted for 44 percent of the quarter’s revenue.

Apple shipped 2,289,000 Macintosh computers during the quarter, representing 51 percent unit growth and 54 percent revenue growth over the year-ago quarter. It sold 10,644,000 iPods during the quarter, representing 1 percent unit growth and 8 percent revenue growth over the year-ago quarter. Quarterly iPhone sales were 1,703,000.

As per another Forbes reports, Apple has promised to sell 10 million iPhones in 2008 on a call with analysts Wednesday. Watch this space, as Apple is surely going to be in news for most of this year.

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