Archive

Archive for the ‘design services’ Category

What does it take to create Silicon Valley!

December 29, 2013 1 comment

I was pointed out to a piece of news on TV, where a ruling chief minister of an Indian state apparently announced that he could make a particular state of India another Silicon Valley! Interesting!!

First, what’s the secret behind Silicon Valley? Well, I am not even qualified enough to state that! However, all I can say is: it is probably a desire to do something very different, and to make the world a better place – that’s possibly the biggest driver in all the entrepreneurs that have come to and out of Silicon Valley in the USA.

If you looked up Wikipedia, it says that the term Silicon Valley originally referred to the region’s large number of silicon chip innovators and manufacturers, but eventually, came to refer to all high-tech businesses in the area, and is now generally used as a metonym for the American high-technology sector.

So, where exactly is India’s high-tech sector? How many Indian state governments have even tried to foster such a sector? Ok, even if the state governments tried to foster, where are the entrepreneurs? Ok, an even easier one: how many school dropouts from India or even smal-time entrepreneurs have even made a foray into high-tech?

Right, so where are the silicon chip innovators from India? Sorry, I dd not even hear a word that you said? Can you speak out a little louder? It seems there are none! Rather, there has been very little to no development in India, barring the work that is done by the MNCs. Correct?
hsinchuOne friend told me that Bangalore is a place that can be Silicon Valley. Really? How?? With the presence of MNCs, he said! Well, Silicon Valley in the US does not have MNCs from other countries, are there? Let’s see! Some companies with bases in Silicon Valley, listed on Wikipedia, include Adobe, AMD, Apple, Applied Materials, Cisco, Facebook, Google, HP, Intel, Juniper, KLA-Tencor, LSI, Marvell, Maxim, Nvidia, SanDisk, Xilinx, etc.

Now, most of these firms have setups in Bangalore, but isn’t that part of the companies’ expansion plans? Also, I have emails and requests from a whole lot of youngsters asking me: ‘Sir, please advice me which company should I join?’ Very, very few have asked me: ‘Sir, I have this idea. Is it worth exploring?’

Let’s face the truth. We, as a nation, so far, have not been one to take up challenges and do something new. The ones who do, or are inclined to do so, are working in one of the many MNCs – either in India or overseas.

So, how many budding entrepreneurs are there in India, who are willing to take the risk and plunge into serious R&D?

It really takes a lot to even conceive a Silicon Valley. It takes people of great vision to build something of a Silicon Valley, and not the presence of MNCs.

Just look at Hsinchu, in Taiwan, or even Shenzhen, in China. Specifically, look up Shenzhen Hi-Tech Industrial Park and the Hsinchu Science Park to get some ideas.

Focus on good power-aware verification strategy for SoCs: Dr. Wally Rhines

January 7, 2013 1 comment

Dr. Wally Rhines.

Dr. Wally Rhines.

It is always a pleasure to chat with Dr. Wally (Walden C.) Rhines, chairman and CEO, of Mentor Graphics. I chatted with him, trying to understand gigascale design, verification trends, strategy for power-aware verification, SERDES design challenges, migrating to 3D FinFET transistors, and Moore’s Law getting to be “Moore Stress”!

Chip design in gigascale, hertz, complex
First, I asked him to elaborate on how implementation of chip design will evolve, with respect to gigascale design, gigahertz and gigacomplex geometries.

He said: “Thanks to close co-operation among members of the foundry ecosystem, as well as cooperation between IDMs and their suppliers, serious development of design methods and software tools is running two to three generations ahead of volume manufacturing capability. For most applications, “Gigascale” power dissipation is a bigger challenge than managing the complexity but “system-level” power optimization tools will continue to allow rapid progress. Thermal analysis is becoming part of the designer’s toolkit.”

Functional verification is continually challenged by complexity but there have been, and continue to be, many orders of magnitude improvement in performance just from adoption of emulation, intelligent test benches and formal methods so this will not be a major limitation.

The complexity of new physical design problems will, however, be very challenging. Design problems ranging from basic ESD analysis, made more complex due to multiple power domains, to EMI, electromigration and intra-die variability are now being addressed with new design approaches. Fortunately, programmable electrical rule checking is being widely adopted and will help to minimize the impact of these physical effects.

Is verification keeping up?
How is the innovation in verification keeping up with trends?

Dr. Rhines added that over the past decade, microprocessor clock speeds have leveled out at 3 to 4 GHz and server performance improvement has come mostly from multi-core architectures. Although some innovative approaches have allowed simulators to gain some advantage from multi-core architectures, the speed of simulators hasn’t kept up with the growing complexity of leading edge chips.

Emulators have more than made up the difference. Emulators offer more than four orders of magnitude faster performance than simulators and emulators do so at about 0.005X the cost per cycle of simulation. The cost of power per year is more than one third the cost of hardware in a large simulation farm today, while emulation offers a 12X savings in power per verification clock cycle. For those who design really complex chips, a combination of emulation and simulation, along with formal methods and intelligent test benches, has become standard.

At the block and subsystem level, high level synthesis is enabling the next move up in design and verification abstraction. Since verification complexity grows at about the square of component count, we have plenty of room to handle larger chips by taking advantage of the four orders of magnitude improvement through emulation plus another three or four orders of magnitude through formal verification techniques, two to three orders of magnitude from intelligent test benches and three orders of magnitude from higher levels of abstraction.

By applying multiple engines and multiple abstraction levels to the challenge of verifying chips, the pressure is on to integrate the flow. Easily transitioning and reusing verification efforts from every level—including tests and coverage models, from high level models to RTL and from simulation to emulation—is being enabled through more powerful and adaptable verification IP and high level, graph-based test specification capabilities. These are keys to driving verification reuse to match the level of design reuse.

Powerful verification management solutions enable the collection of coverage information from all engines and abstraction levels, tracking progress against functional specifications and verification plans. Combining verification cycle productivity growth from emulation, formal, simulation and intelligent testing with higher verification abstraction, re-use and process management provides a path forward to economically verifying even the largest, most complex chips on time and within budget.

Good power-aware verification strategy for SoCs
What should be a good power-aware verification strategy for SoCs

According to him, the most important guideline is to start power-aware design at the highest possible level of system description. The opportunity to reduce system power is typically an order of magnitude greater at the system level than at the RTL level. For most chips today, that means at least the transaction level when the design is still described in C++ or SystemC.

Significant experience and effort should then be invested at the RTL level using synthesis and UPF-enabled simulation. Verification solutions typically automate the generation of correctness checks for power-control sequences and power-state coverage metrics. As SoC power is typically managed by software, the value of a hardware/software co-verification and co-debug solution in simulation and emulation becomes apparent in power-management verification at this level.

As designers proceed to the gate and transistor level, accuracy of power estimation improves. That is why gate level analysis and verification of the fully implemented power management architecture is important. Finally, at the physical layout, designers traditionally were stuck with whatever power budget was passed down to them. Now,they increasingly have power goals that can be achieved using dozens of physical design techniques that are built into the place and route tools.
Read more…

Ph.D candidates in VLSI industry! Is enough being done?


“Fine art is that in which the hand, the head, and the heart of man go together.” – John Ruskin.

“Great men’s honor ought always to be measured by the methods they made use of in attaining it.” – François Duc De La Rochefoucauld.

The 26th International Conference on VLSI Design 2013 is starting tomorrow at Hyatt Regency, Pune. Over the years, it has served as a forum for VLSI folks to discuss topics related to VLSI design, EDA, embedded systems, etc. The theme for the VLSI and embedded systems conference is green technology.

That brings me to a point raised by one reader of this blog- what’s the future of  Ph.D candidates in the VLSI industry! First, do not believe when you are told that you can only join academics in case you are a Ph.D. You can certainly switch over to R&D at the various VLSI companies! Or, you can start on your own, by developing something noteworthy!!

As for the current scenario, especially in India, students, or well, Ph.D holders should seriously consider developing useful projects for  use in India, and globally. It seems all too very easy for folks to join some large MNC in India or overseas, as according to such people: their jobs are done!

For some strange reason, semiconductor/VLSI development seems to have remained in the backburner in India! I was surprised on visiting a center in Bangalore to find students – actually, some Ph.D. holders – working on projects that may never even see the light of the day! That leads to the question: are the tutors guiding them enough? Do we even have systems in place that backs development?

Having spent a long time in the Far East, I have seen young Chinese and Taiwanese, Korean and Japanese men and women take to VLSI earnestly. How did they manage to do that? Mainly, by starting their own companies and developing some product!

Now, this is something not yet evident in India! Has anyone else asked this question? And, can the Indian VLSI community make this happen? It should not be very difficult, if the head, hand and heart are there in the deed!

As John Ruskin says, “Fine art is that in which the hand, the head, and the heart of man go together.”

François Duc De La Rochefoucauld. says, “Great men’s honor ought always to be measured by the methods they made use of in attaining it.”

Hope these words make sense! Developing and designing solutions is a fine art where the hand, the head and the heart must be in sync. And, if you have really developed a solution or a product, what were the methods you used to attain that! Answering these two questions are tough, but the answers really lie within us!

My question remains: do students (in India) really spend time for developing projects, or do they simply copy or buy projects?

Coming back to the VLSI conference, this year’s program will play host to the 4th IEEE International Workshop on Reliability Aware System Design and Test (RASDAT) as well. There will be discussions around topics such as design-for-test, fault-tolerant micro architecture, low power test, reliability of CMOS circuits, design for reliability, dependability and verifiability, etc.

A semiconductor company will likely be introducing a portable and affordable analog design kit. Students will no longer be required to go to expensive labs for developing projects. There should be lot of simulation tools, online course materials, community support, lab materials, etc. to use using the analog design kit. There should be a string of announcements too, so let’s wait for the event to start!

Round-up 2009: Best of EDA, embedded systems and software, design trends

December 29, 2009 Comments off

Friends, the next installment in this series on the round-up of 2009 lists my top posts across three specific fields that are very important within the semiconductor industry — electronic design automation (EDA), embedded systems and software, and some design trends. Here you go!

EDA

Synopsys on Discovery 2009, VCS2009 and CustomSIM

State of global semicon industry: Hanns Windele, Mentor

New routing tool likely to cover upcoming MCMM challenges: Hanns Windele, Mentor

Cadence’s focus — systems, low power, enterprise verification, mixed signal and advanced nodes

Zebu-Server — Enterprise-type emulator from EVE

State of the global EDA industry: Dr. Pradip Dutta, Synopsys

Mentor’s Wally Rhines on global EDA industry and challenges

Mentor’s Wally Rhines on EDA industry — II

Cadence’s Lip-Bu Tan on global semicon, EDA and Indian semicon industry

Indian EDA thought leaders can exploit opportunities from tech disruption!

EMBEDDED SYSTEMS & SOFTWARE

Top 10 embedded companies in India — By the way, this happens to be the most read article of the year!

NI LabView solves embedded and multicore problems!

Intel’s retail POS kiosk provides unique shopping experience

ISA Vision Summit 2009: Growing influence of embedded software on hardware world

MCUs are now shaping the embedded world!

Embedded electronics: Trends and opportunities in India!

Growth drivers for embedded electronics in India

DESIGN TRENDS

Microcontrollers unplugged! How to choose an MCU

Xilinx rolls out ISE Design Suite 11 for targeted design platforms!

TI’s 14-bit ADC unites speed and efficiency

ST/Freescale intro 32-bit MCUs for safety critical applications

Again, I am certain to have missed out some posts that you may have liked. If yes, please do point out. Also, it is not possible for me to select the top 10 articles for the year. If anyone of you can, I’d be very delighted.

My best wishes to you, your families and loved ones for a happy and prosperous 2010.

P.S.: The next two round-ups will be on solar photovoltaics and semiconductors. These will be added tomorrow, before I disappear for the year! 😉

%d bloggers like this: