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Agnisys makes design verification process extremely efficient!


Agnisys Inc. was established in 2007 in Massachusetts, USA, with a mission to deliver innovative automation to the semiconductor industry. The company offers affordable VLSI design and verification tools for SoCs, FPGAs and IPs that makes the design verification process extremely efficient.

Agnisys’ IDesignSpec is an award winning engineering tool that allows an IP, chip or system designer to create the register map specification once and automatically generate all possible views from it. Various outputs are possible, such as UVM, OVM, RALF, SystemRDL, IP-XACT etc. User defined outputs can be created using Tcl or XSLT scripts. IDesignSpec’s patented technology improves engineer’s productivity and design quality.

The IDesignSpec automates the creation of registers and sequences guaranteeing higher quality and consistent results across hardware and software teams. As your ASIC or FPGA design specification changes, IDesignSpec automatically adjusts your design and verification code, keeping the critical integration milestones of your design engineering projects synchronized.

Register verification and sequences consume up to 40 percent of project time or more when errors are the source of re-spins of SoC silicon or an increase in the number of FPGA builds. IDesignSpec family of products is available in various flavors such as IDSWord, IDSExcel, IDSOO and IDSBatch.

IDesignSpec more than a tool for creating register models!
Anupam Bakshi, founder, CEO and chairman, Agnisys, said: “IDesignSpec is more than a tool for creating register models. It is now a complete Executable Design Specification tool. The underlying theme is always to capture the specification in an executable form and generate as much code in the output as possible.”

The latest additions in the IDesignSpec are Constraints, Coverage, Interrupts, Sequences, Assertions, Multiple Bus Domains, Special Registers and Parameterization of outputs.

“IDesignSpec offers a simple and intuitive way to specify constraints. These constraints, specified by the user, are used to capture the design intent. This design intent is transformed into code for design, verification and software. Functional Coverage models can be automatically generated from the spec so that once again the intent is captured and converted into appropriate coverage models,” added Bakshi.

Using an add-on function of capturing Sequences, the user is now able to capture various programming sequences in the spec, which  are translated into C++ and UVM sequences, respectively. Further, the interrupt registers can now be identified by the user and appropriate RTL can be generated from the spec. Both edge sensitive and level interrupts can be handled and interrupts from various blocks can be stacked.

Assertions can be automatically generated from the high level constraint specification. These assertions can be created with the RTL or in the external files such that they can be optionally bound to the RTL. Unit level assertions are good for SoC level verification and debug, and help the user in identifying issues deep down in the simulation hierarchy.

The user can now identify one or more bus domains associated with Registers and Blocks, and generate appropriate code from it. Special Registers such as shadow registers and register aliasing is also automatically generated.

Finally all of the outputs such as RTL, UVM, etc., can be parameterized now, so that a single master specification can be used to create outputs that can be parameterized at the elaboration time.

How is IDesignSpec working as chip-level assertion-based verification?

Bakshi said: “It really isn’t an assertion tool! The only assertion that we automatically generate is from the constraints that the user specifies. The user does not need to specify the assertions. We transform the constraints into assertions.”
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Students, show off your technical talent @ Mentor’s University Design Contest 2010!


I really envy the students of today! They live in such lucky times!! There are so many opportunities for them to learn, grow and flourish, and so many avenues to venture!!!

Here’s one more opportunity for those brilliant students from various engineering colleges across India.  Friends, you can participate and show off your techical talent by participating in Mentor Graphics’ University Design Contest 2010!

Veeresh Shetty, Mentor Graphics.

Mentor's Veeresh Shetty.

I was elated when Veeresh Shetty of Mentor Graphics informed me today about this great contest!  Thanks a lot, Veeresh, and Mentor Graphics India, especially, my friend Raghu Panicker, for taking time to think about spotting talent among students.

Time to participate and win, dear students!
First, what do the students get out of this contest? Well, there’s prize money involved! The top three winners will earn a Certificate of Recognition. There will be one Winner team followed by two runner-up teams. The winning team will be awarded a cash prize of $3,000, 1st Runner-up – $2,000 and 2nd Runner-up – $1,000, respectively.

So, what’s the purpose behind this contest? Well, this is the inaugural Mentor Graphics University Design contest 2010 in India.

The objective/focus of this contest is to provide an opportunity for engineering students to showcase their technical talent and competency using Mentor Graphics tools. The company expects to grow this contest with increased representation and participation, and draw maximum number of contestants. Read more…
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