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Agnisys makes design verification process extremely efficient!


Agnisys Inc. was established in 2007 in Massachusetts, USA, with a mission to deliver innovative automation to the semiconductor industry. The company offers affordable VLSI design and verification tools for SoCs, FPGAs and IPs that makes the design verification process extremely efficient.

Agnisys’ IDesignSpec is an award winning engineering tool that allows an IP, chip or system designer to create the register map specification once and automatically generate all possible views from it. Various outputs are possible, such as UVM, OVM, RALF, SystemRDL, IP-XACT etc. User defined outputs can be created using Tcl or XSLT scripts. IDesignSpec’s patented technology improves engineer’s productivity and design quality.

The IDesignSpec automates the creation of registers and sequences guaranteeing higher quality and consistent results across hardware and software teams. As your ASIC or FPGA design specification changes, IDesignSpec automatically adjusts your design and verification code, keeping the critical integration milestones of your design engineering projects synchronized.

Register verification and sequences consume up to 40 percent of project time or more when errors are the source of re-spins of SoC silicon or an increase in the number of FPGA builds. IDesignSpec family of products is available in various flavors such as IDSWord, IDSExcel, IDSOO and IDSBatch.

IDesignSpec more than a tool for creating register models!
Anupam Bakshi, founder, CEO and chairman, Agnisys, said: “IDesignSpec is more than a tool for creating register models. It is now a complete Executable Design Specification tool. The underlying theme is always to capture the specification in an executable form and generate as much code in the output as possible.”

The latest additions in the IDesignSpec are Constraints, Coverage, Interrupts, Sequences, Assertions, Multiple Bus Domains, Special Registers and Parameterization of outputs.

“IDesignSpec offers a simple and intuitive way to specify constraints. These constraints, specified by the user, are used to capture the design intent. This design intent is transformed into code for design, verification and software. Functional Coverage models can be automatically generated from the spec so that once again the intent is captured and converted into appropriate coverage models,” added Bakshi.

Using an add-on function of capturing Sequences, the user is now able to capture various programming sequences in the spec, which  are translated into C++ and UVM sequences, respectively. Further, the interrupt registers can now be identified by the user and appropriate RTL can be generated from the spec. Both edge sensitive and level interrupts can be handled and interrupts from various blocks can be stacked.

Assertions can be automatically generated from the high level constraint specification. These assertions can be created with the RTL or in the external files such that they can be optionally bound to the RTL. Unit level assertions are good for SoC level verification and debug, and help the user in identifying issues deep down in the simulation hierarchy.

The user can now identify one or more bus domains associated with Registers and Blocks, and generate appropriate code from it. Special Registers such as shadow registers and register aliasing is also automatically generated.

Finally all of the outputs such as RTL, UVM, etc., can be parameterized now, so that a single master specification can be used to create outputs that can be parameterized at the elaboration time.

How is IDesignSpec working as chip-level assertion-based verification?

Bakshi said: “It really isn’t an assertion tool! The only assertion that we automatically generate is from the constraints that the user specifies. The user does not need to specify the assertions. We transform the constraints into assertions.”
Read more…

Algotochip building ecosystem with IP providers in targeted markets


Satish Padmanabhan.

Satish Padmanabhan.

Algorithm-to-chips is Algotochip’s mission. It turns algorithms into chips by converting your behavioral algorithm C-code into architecture C-code into RTL into GDS-II.

Speaking about architecture evolution at the 13th Global Electronics Summit at Santa Cruz, USA, Satish Padmanabhan, CTO and founder, Algotochip, said that the interconnect between CPU and all the HA blocks needs to be determined.

The market approach includes building an ecosystem with leading IP providers in targeted markets. Some areas Algotochip is looking at are LTE and smart grid markets.

Nitto Denko is committed to support Algotochip moving forward. Year 2013 will see significant investment increases in terms of engineering resources, as well as sales and marketing organization to cover USA, China and Japan.

Algotochip is showing that its technology is sound in improving system hardware and software partitioning and first time right design. The LTE turbo decoder performances in terms of throughput, power and gates count is showing the benefits of Algotochip BlueBox. The company is now building an ecosystem around its technology.

ARM Holdings and Tensilica are the first of the few partners that Algotochip wants to collaborate with to improve the overall time-to-market of digital design of the SoC, ASIC and FPGA, etc.

Students, show off your technical talent @ Mentor’s University Design Contest 2010!


I really envy the students of today! They live in such lucky times!! There are so many opportunities for them to learn, grow and flourish, and so many avenues to venture!!!

Here’s one more opportunity for those brilliant students from various engineering colleges across India.  Friends, you can participate and show off your techical talent by participating in Mentor Graphics’ University Design Contest 2010!

Veeresh Shetty, Mentor Graphics.

Mentor's Veeresh Shetty.

I was elated when Veeresh Shetty of Mentor Graphics informed me today about this great contest!  Thanks a lot, Veeresh, and Mentor Graphics India, especially, my friend Raghu Panicker, for taking time to think about spotting talent among students.

Time to participate and win, dear students!
First, what do the students get out of this contest? Well, there’s prize money involved! The top three winners will earn a Certificate of Recognition. There will be one Winner team followed by two runner-up teams. The winning team will be awarded a cash prize of $3,000, 1st Runner-up – $2,000 and 2nd Runner-up – $1,000, respectively.

So, what’s the purpose behind this contest? Well, this is the inaugural Mentor Graphics University Design contest 2010 in India.

The objective/focus of this contest is to provide an opportunity for engineering students to showcase their technical talent and competency using Mentor Graphics tools. The company expects to grow this contest with increased representation and participation, and draw maximum number of contestants. Read more…

Round-up 2009: Best of EDA, embedded systems and software, design trends

December 29, 2009 Comments off

Friends, the next installment in this series on the round-up of 2009 lists my top posts across three specific fields that are very important within the semiconductor industry — electronic design automation (EDA), embedded systems and software, and some design trends. Here you go!

EDA

Synopsys on Discovery 2009, VCS2009 and CustomSIM

State of global semicon industry: Hanns Windele, Mentor

New routing tool likely to cover upcoming MCMM challenges: Hanns Windele, Mentor

Cadence’s focus — systems, low power, enterprise verification, mixed signal and advanced nodes

Zebu-Server — Enterprise-type emulator from EVE

State of the global EDA industry: Dr. Pradip Dutta, Synopsys

Mentor’s Wally Rhines on global EDA industry and challenges

Mentor’s Wally Rhines on EDA industry — II

Cadence’s Lip-Bu Tan on global semicon, EDA and Indian semicon industry

Indian EDA thought leaders can exploit opportunities from tech disruption!

EMBEDDED SYSTEMS & SOFTWARE

Top 10 embedded companies in India — By the way, this happens to be the most read article of the year!

NI LabView solves embedded and multicore problems!

Intel’s retail POS kiosk provides unique shopping experience

ISA Vision Summit 2009: Growing influence of embedded software on hardware world

MCUs are now shaping the embedded world!

Embedded electronics: Trends and opportunities in India!

Growth drivers for embedded electronics in India

DESIGN TRENDS

Microcontrollers unplugged! How to choose an MCU

Xilinx rolls out ISE Design Suite 11 for targeted design platforms!

TI’s 14-bit ADC unites speed and efficiency

ST/Freescale intro 32-bit MCUs for safety critical applications

Again, I am certain to have missed out some posts that you may have liked. If yes, please do point out. Also, it is not possible for me to select the top 10 articles for the year. If anyone of you can, I’d be very delighted.

My best wishes to you, your families and loved ones for a happy and prosperous 2010.

P.S.: The next two round-ups will be on solar photovoltaics and semiconductors. These will be added tomorrow, before I disappear for the year! 😉

How Intel manages IT through downturn — Server and data center optimization!

September 15, 2009 Comments off

Ever wondered how Intel is managing IT through the downturn — Server and data center optimization? According to Kenny Sng, data center engineering manager, Intel Technology Asia Pte Ltd, there are three key things that Intel IT does. These are:

• Internal efficiencies are critical in freeing up resources and reducing operational costs.

• Server refresh is a key strategy to ensure IT runs efficiently.

• Intel continues to look at innovation in DC operations for reducing running costs

Server and data center optimization? Intel's Kenny Sng, data center engineering manager, making a point!

Server and data center optimization? Intel's Kenny Sng, data center engineering manager, making a point!

How can IT make a difference?

* Drive employee productivity — by way of mobile client refresh

* Drive business productivity

* Continue IT efficiencies — by way of data center and server refresh

Intel data center profile

Intel has four major groups currently driving individual data center requirements (DOME).

Design:

Support the chip design community

Design Computing: Has most of the servers in Intel

Office:

Supporting typical IT and customer services

General Purpose

Manufacturing:

Manufacturing computing supporting fabrication and assembly

FAB/ATM

Enterprise:

Enterprise applications supporting eBiz and ERP

About 80 percent of servers in Intel are in D. And, 20 percent of servers in Intel are in O, M and E, categories.

Intel IT’s approach to data center optimization

Intel’s approach is very simple — standardize, improve and optimize.

Standardize

* Supply and demand forecasting

* Processes and design specs

* Overall data center structure

All of this  enables IT and consolidations, prevents unnecessary spending and ensures consistency in the overall data center structure.

Improve

* Batch processing pools via grid computing (DCV) – (D)

* Virtualization (DCU) – (O) & (E)

* Replace single core with quad-core servers

* Information Lifecycle Management

* Intel “Green” data center initiatives

* Containerized Data Centers

These go on to reduce server spending and storage/hardware expenses, Contain costs (network, power, space), simplify the environment and well, improve energy efficiency by at least 6x.

Optimize

* Close inefficient and unnecessary data centers

* Assure batch and virtualized servers are in optimal data center locations

What do these do? One, maximize data center utilization in all locations, and two, maximize server asset utilization across the world. Read more…

TI Beagle Board for Indian open source developers and hobbyists

October 18, 2008 Comments off

Texas Instruments recently introduced the pocket-size, USB-powered Beagle Board based on TI’s OMAP3530 applications processor. It features an ARM Cortex-A8 core, 2D/3D graphics engine and high-performance TMS320C64x+ digital signal processor (DSP) core.

This will help open source developers and hobbyists in India to realize their creative design ideas without being restricted by expensive hardware development tools, lackluster performance capabilities, high power consumption or stifled design environments, according to Khasim Syed Mohammed, Lead Developer for Open Platforms, Texas Instruments India Pvt. Ltd.

He added: “It helps us in learning cutting edge technology, innovating new ideas and executing them. Beagle board should be used to explore the growing demand in areas like medical, security, infotainment, navigation, education, signal processing, mobile devices and communication.”

Important for India
This initiative is particularly important in India where students can use the board to learn, show case their efforts and global recognition for their innovations.

Innovators in India should use this opportunity to prototype their ideas using the specification software hardware openly available in a never before package. It is important for the student community to learn new technologies, explore new areas and innovate. This initiative by TI also helps startups in India who want to explore the OMAP hardware but have limited support base for their requirements.

Passionate open source developers and hobbyists in India can realize their creative design ideas without being restricted by expensive hardware development tools, lackluster performance capabilities, high power consumption or stifled design environments.

Open platform innovators have the expandability of desktop machines without the expense, bulk or noise with the Beagle board, which is a powerful, low-cost and fan-less embedded system development board smaller than the size of an index card.

Board named after Beagle
The board is named after a popular breed of dogs, Beagle. It has been designed it to be one of the shortest pocket sized OMAP3530 boards. TI is encouraging the Open community to treat this as a pet, which is easy to carry and can be USB powered so that development is made easy and can perform high end applications at very less power.

Inspired to create a small, open source development board, a small group of enthusiastic engineers worked together on the concept and realization of the Beagle board. The resulting 3×3-inch board bridges desktop and embedded development by allowing developers to use the same peripherals and usage mode for almost limitless expansion. Developers are able to design exactly according to their specifications and collaborate with the community on creative new applications.

Mohammed said: “There is a growing need for development support in the Open Community. The Open Community is capable and passionate to work on industry’s high end processors and architectures and build innovative applications and prototypes for mobile, portable infotainment, portable navigation, medical, home security and many such applications. Another important reason for this initiative was the cost implications in owning a high end platform which was restricting them in exploring many such ideas/applications.”

Beagleboard is a global initiative to address the growing needs of the Open community to help them innovate and explore new areas by providing them access to leading hardware and software, giving them a forum to present their views and thoughts, showcasing their efforts for global appreciation, maintain community’s contribution.

Developers can quickly maximize their design concepts by tapping into the expertise and support of some of the industry’s top Linux programmers already experimenting with the Beagle board. With communities hosting the latest updates and codes, live forums and chats for easy collaboration, developers have easy access to support and exchange of ideas. Users are encouraged to join active, existing communities already participating in the project.

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