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Agnisys makes design verification process extremely efficient!


Agnisys Inc. was established in 2007 in Massachusetts, USA, with a mission to deliver innovative automation to the semiconductor industry. The company offers affordable VLSI design and verification tools for SoCs, FPGAs and IPs that makes the design verification process extremely efficient.

Agnisys’ IDesignSpec is an award winning engineering tool that allows an IP, chip or system designer to create the register map specification once and automatically generate all possible views from it. Various outputs are possible, such as UVM, OVM, RALF, SystemRDL, IP-XACT etc. User defined outputs can be created using Tcl or XSLT scripts. IDesignSpec’s patented technology improves engineer’s productivity and design quality.

The IDesignSpec automates the creation of registers and sequences guaranteeing higher quality and consistent results across hardware and software teams. As your ASIC or FPGA design specification changes, IDesignSpec automatically adjusts your design and verification code, keeping the critical integration milestones of your design engineering projects synchronized.

Register verification and sequences consume up to 40 percent of project time or more when errors are the source of re-spins of SoC silicon or an increase in the number of FPGA builds. IDesignSpec family of products is available in various flavors such as IDSWord, IDSExcel, IDSOO and IDSBatch.

IDesignSpec more than a tool for creating register models!
Anupam Bakshi, founder, CEO and chairman, Agnisys, said: “IDesignSpec is more than a tool for creating register models. It is now a complete Executable Design Specification tool. The underlying theme is always to capture the specification in an executable form and generate as much code in the output as possible.”

The latest additions in the IDesignSpec are Constraints, Coverage, Interrupts, Sequences, Assertions, Multiple Bus Domains, Special Registers and Parameterization of outputs.

“IDesignSpec offers a simple and intuitive way to specify constraints. These constraints, specified by the user, are used to capture the design intent. This design intent is transformed into code for design, verification and software. Functional Coverage models can be automatically generated from the spec so that once again the intent is captured and converted into appropriate coverage models,” added Bakshi.

Using an add-on function of capturing Sequences, the user is now able to capture various programming sequences in the spec, which  are translated into C++ and UVM sequences, respectively. Further, the interrupt registers can now be identified by the user and appropriate RTL can be generated from the spec. Both edge sensitive and level interrupts can be handled and interrupts from various blocks can be stacked.

Assertions can be automatically generated from the high level constraint specification. These assertions can be created with the RTL or in the external files such that they can be optionally bound to the RTL. Unit level assertions are good for SoC level verification and debug, and help the user in identifying issues deep down in the simulation hierarchy.

The user can now identify one or more bus domains associated with Registers and Blocks, and generate appropriate code from it. Special Registers such as shadow registers and register aliasing is also automatically generated.

Finally all of the outputs such as RTL, UVM, etc., can be parameterized now, so that a single master specification can be used to create outputs that can be parameterized at the elaboration time.

How is IDesignSpec working as chip-level assertion-based verification?

Bakshi said: “It really isn’t an assertion tool! The only assertion that we automatically generate is from the constraints that the user specifies. The user does not need to specify the assertions. We transform the constraints into assertions.”
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Next wave of design challenges, and future growth of EDA: Dr. Wally Rhines

December 15, 2012 1 comment

Dr. Wally Rhines.

Dr. Wally Rhines.

Today, EDA requires specialization. Elaborating on EDA over the past decade, Dr. Walden (Wally) C. Rhines, chairman and CEO, of Mentor Graphics, and vice chairman of the EDA Consortium, USA, said that PCB design has been flat despite growth in analysis, DFM and new emerging markets. Front end design has seen growth from RF/analog design and simulation, and analysis As design methodologies mature, EDA expenditures stop growing. He was speaking at Mentor Graphics’ U2U (User2User) conference in Bangalore, India.

Most of the EDA revenue growth comes from major new design methodologies, such as ESL, DFM, analog-mixed signal and RF. PCB design trend continues to be flat, and includes license and maintenance. The IC layout verification market is pointing to a 2.1 percent CAGR at the end of 2011. The RTL simulation market has been growing at 1.3 percent CAGR for the last decade. The IC physical implementation market has been growing at 3,4 percent CAGR for the last decade.

Growth areas in EDA from 2000-2011 include DFM at 28 percent CAGR, formal verification at 12 percent, ESL at 11 pecent, and IC/ASIC analysis at 9 percent, respectively.

What will generate the next wave of electronic product design challenges, and the future growth of EDA? This would involve solving new problems that are not part of the traditional EDA, and ‘do what others don’t do!

Methodology changes that may change EDA
There are five factors that can make this happen. These are:
* Low power design beyond RTL (and even ESL).
* Functional verification beyond simulation.
* Physical verification beyond design for manufacturability.
* Design for test beyond compression.
* System design beyond PCBs

Low power design at higher levels
Power affects every design stage. Sometimes, designing for low power at system level is required. System level optimization has the biggest impact on power/performance. And, embedded software is a major point of leverage.

Embedded software has an increasing share of the design effort. Here, Mentor’s Nucleus power management framework is key. It has an unique API for power management, enables software engineers to optimize power consumption, and reduces lines of application code. Also, power aware design optimizes code efficiency.

Functional verification beyond RTL simulation
The Verification methodology standards war is over. UVM is expected to grow by 286 percent in the next 12 months. Mentor Graphics Questa inFact is the industry’s most advanced testbench automation solution. It enables Testbench re-use and accelerates time-to-coverage. Intelligent test bench facilitates linear transition to multi-processing.

Questa accelerates the hardware/software verification environment. In-circuit emulation has been evolving to virtual hardware acceleration and embedded software development. Offline debug increases development productivity. A four-hour on-emulator software debug session drops to 30 minutes batch run. The offline debug allows 150 software designers to jumpstart debug process on source code. Virtual stimulus increases the flexibility of the emulator. As an example, Veloce is 700x more efficient than large simulation farms.

Physical verification beyond design for manufacturability
The Calibre PERC is a new approach to circuit verification. The Calibre 3DSTACK is the verification flow for 3D.
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No real fun being at DAC or ESC! Seriously!!

May 1, 2011 Comments off

The 48th Design Automation Conference (DAC) kicks off in about a month’s time in San Diego, California, USA. I have been flooded with invites. There’s also an Embedded Systems Conference starting tomorrow, in San Jose. However, I will give both of the events a miss! Why? Simply because of one fact! The EDA industry has stopped surprising me! And, so has the embedded systems industry!!

I an very well aware of the changing and ‘challenging’ trends in the global semiconductor industry. I should also add that I do have at least some knowledge of the global EDA industry in 2010 and its expectations for 2011.

I am aware of the fact that product lifecycle management involves reducing the time-to-market cycles for new product introduction. Industry folks have, time and again, apprised me of the fact that there is a need to bridge the gap between software and hardware – and growing the IT and VLSI industries.

Cadence, for instance, will share a new technology that addresses some of the toughest challenges detailed in the EDA360 vision at ESC 2011. For how long will the challenges be met? Synopsys seems to be raking in the dollars, year after year. Mentor, despite its ‘current issues’, has been doing fairly well. So, what’s new over here?

In embedded, it is very well known globally, that India is an emerging leader. Otherwise, there is hardly any electronics or semiconductor related manufacturing happening in India, despite the best efforts of the ISA.

So, why isn’t all of this being viewed as industry growth? Maybe, you have all the answers! I will only try to sound more optimistic, without creating additional pain!

Almost all of the new techniques and technologies to be announced at either conference, will or already have made their way to India. Or, the companies using them are not allowed to speak about them, at best!

Mentor’s Wally Rhines on EDA industry — II

September 30, 2009 1 comment

Friends, this is a continuation of my conversation with Walden (Wally) C. Rhines, chairman and CEO, Mentor Graphics Corp., who was recently on a visit to India for the EDA Tech Forum as keynoter.

Software-to-silicon verification

Today there’s a growing focus on software-to-silicon verification, encompassing a full range of challenges that also includes embedded software, system validation and integration testing. How true?

Certainly true! The problem of hardware/software codesign and co-verification has been around a long time but, until this decade, generated less than $50million of annual EDA revenue.

Rhines said: “This decade, the market has grown rapidly and companies like Mentor have experience accelerated revenue growth in both their ESL design environments and their embedded software development tools and technology. Emulation has grown increasingly popular to verify not only hardware but to test application/embedded software.

“And, embedded software development tools, technology, RTOS, protocol stacks and LINUX middleware have all become part of the electronic product developers design environment.”

EDA in modeling and photomask correction

How and where does EDA fit into the big picture, particularly in the areas of modeling and photomask correction?

According to Rhines, for photomask correction, the EDA industry is the only provider, with two large EDA companies providing more than 90 percent of the optical proximity correction revenue.

“EDA companies have changed over the last decade due to the growth of OPC and DFM. Wafer fabs have now become major customers. Specialists in optics have joined traditional electronic design specialists at EDA companies to create the key technologies. EDA companies are now leading the way in the development of new process technology as evidenced by the IBM/Mentor joint development program at 22nm, he added. Read more…

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