Archive for the ‘FPGA design’ Category

Plunify’s InTime helps FPGA design engineers meet timing and area goals!

Kirvy Teo

Kirvy Teo

Engineers designing FPGA applications face many challenges. Using Plunify’s automation and analysis platform, engineers can run 100 times more builds, analyze a larger set of builds and quickly zoom in on better quality results. Using data analytics and the cloud, Plunify created new capabilities for FPGA design, with InTime being an example.

Kirvy Teo said: What happens when you need to close timing in FPGA design and still can’t get it to work? Here is a new way to solve that problem – machine learning and analytics. InTime is an expert software that helps FPGA design engineers meet timing and area goals by recommending “strategies”. Strategies are combination of settings found in the existing FPGA software. With more than 70 settings available in the FPGA software, no sane FPGA design engineer have the time or capacity to understand how these affect the design outcomes.

One of the common methods now is to try random bruteforce using seeds. This is a one-way street. If you get to your desired result, great! If not, you would have wasted a bunch of time running builds with you none the wiser. Another aspect of running seeds is that the variance of the results is usually not very big, meaning you can’t run seeds on a design with bad timing scores.

However, using InTime, all builds become part of the data that we used to recommend strategies that can give you better results, using machine learning and predictive analytics. This means you will definitely get a better answer at the end of the day, and we have seen 40 percent performance improvements on designs!

How has Plunify been doing this year so far? According to Teo, Plunify did a controlled release to selected customers in first quarter of 2014, who are mainly based in China. It is easier to guess who as we nicknamed them “BCC” – Big Chinese Corporations.

Unsurprisingly, they have different methodologies to solving timing problems and design guidelines, many of which were done to pre-empt timing problems at the later stage of the design. InTime was a great way to help them to achieve their performance targets without disrupting their tool flows.

Plunify is announcing the launch of InTime during DAC and will be looking to partner with sale organizations in US.

What’s the future path likely to be? Teo added: “Machine learning and predictive analytics are one of the hottest topics and we have yet seen it being used much in chip design. We see a lot of potential in this sector. Beyond what InTime is doing now, there are still many chip design problems that can be solved with similar techniques.

“First, there is a need to determine the type of problems that can be solved with these techniques. Second, we are re-looking at existing design problems and wondering, if I can throw 100 or 1000 machines to this problem, can I get a better result? Third, how to get that better result without even running it!

“As you know, we do offer a FPGA cloud platform on Amazon. One of the most surprising observations is that people do not know how to use all those cheap power in the cloud! FPGA design is still confined to a single machine for daily work, like email. Even if I give you 100 machines, you don’t know how to check your emails faster! We see the same thing, the only method they know is to run seeds. InTime is what they need to make use of all these resources intelligently.

Why would FPGA providers take up the solution?

The InTime software works as a desktop software which can be installed in internal data centers or desktops. It is on longer just a cloud play. It works with the current  in-house FPGA software that the customer already own. We are helping FPGA providers like Xilinx or Altera, by helping their customers with the designs. They will feel: How about “Getting better results without touching your RTL code!”


Xilinx announces 20nm All Programmable UltraSCALE portfolio

December 11, 2013 Comments off

Xilinx Inc. has announced of its 20nm All Programmable UltraScale portfolio with product documentation and Vivado Design Suite support.

Neeraj Varma, director-Sales, India, Xilinx, said: “We are enabling All Programmable and smarter systems. We are using smart IP. We are aligning to produce smarter systems. We are helping customers to differentiate their products faster.

“In future, we will go with concurrent nodes with FPGAs, SoCs and 3D ICs. As per our estimates, 28nm will have a very long life. We shipped the 20nm device in early Nov. 2013. It complements 28nm or new high-performance architectures. 16nm complements 20nm with FinFET, multiprocessing, memory.”

Virtex UltraScale device.

Virtex UltraScale device.

Strategy execution has kept Xilinx a generation ahead. As of Dec. 2013, its 20nm portfolio is available to customers. There are two major announcements from Xilinx.

* Xilinx 20nm All Programmable UltraScale portfolio now available with ASIC-class architecture and ASIC-strength design solution.

* Xiilinx doubles industry’s highest capacity device to 4.4 mn logic, delivering density adantage, a full generation ahead.

KINTEX UltraSCALE – XCKU035, 040, 060, 075, 100, 115.
VIRTEX UltraSCALE – XCVU065, 080, 095, 125, 145, 160.

There is a family migration path. There is scalability for derivative applications. You can leverage PCB investment across platforms. It is future-proof with migration path to 16nm. For making these happen, Xilinx is using the TSMC 20SoC.

Varma added, “We have increased the logic cells in Kintex and Virtex, and added 100G Ethenet blocks and 150G Interlaken blocks.”

The second announcement – highest density in FPGAs in industry. The XCVU440 is the largest in the industry by 4X, a full generation ahead, and uses 50M equivalent ASIC gates. Xilinx is delivering an ASIC-class advantage through silicon, tools and methodology.

There is UltraSCALE ASIC-class architecture, and ASIC-class capabilities. There is also the Vivado ASIC-strength design suite.
UltraFAST is the design methodology. UltraSCALE will support networking, digital video and wireless.

Interconnect bottlenecks impede next generation performance.
* Routing delay dominates overall delay.
* Clock skew consumes more timing margin.
* Sub-optimal CLB packing reduces performance and utilization.

Varma added: “We have solved these issues – as UltraSCALE re-architects the core. There is 90 percent utilization now with maximum performance. We added next-generation routing, ASIC-like clocking – have clocks by segment, and logic cell packing.

“Block-level innovations optimize critical paths for massive bandwidth and processing. We are going to support DDR4, and there will be a lot more security features.”

The Vivado design suite accelerates productivity. Analytical placer solves the interconnect issue.

UltraSCALE apps include:
VIRTEX: 400G OTN switching, 400G transponder, 400G MAC-to-Interlaken bridge, 2x100G Muxponder, ASIC prototyping.
KINTEX: 4×4 mixed mode radio, 100G traffic manager NIC, super high-vision processing, 256-channel ultrasound, 48-channel T/R radar processing.

FPGA design heads to the cloud!

December 6, 2012 3 comments

Han Hua Ng

Harn Hua Ng

Singapore based Plunify claims that chip design companies can design faster and better using cloud computing. Stressing on the company’s go-to-market strategy, Plunify’s founder, Harn Hua Ng, said the Plunify partners with tool vendors, their distributors and complementary sales representatives.

Since pay-as-you-go business models are rare in the semiconductor industry, we went through several steps, of which the first was to better understand the market, the available tools and stake-holders:
* How is the market reacting to cloud computing and licensing schemes?
* What are current tool capabilities with regards to multiple CPUs/servers? Which parts of the chip design workflow can best take advantage of scalable, parallel features?
* What tools are more suitable for a cloud environment?

With these in mind, the next step was to build the cloud platform and the application clients to address immediate concerns – security, accessibility and cost.

“Then, we partner with tool vendors, their distributors and sales reps to bring our solutions to end-users. Companies of different sizes Plunify
view the advantages of cloud computing differently, so solutions need to be customized accordingly. Some see Plunify as solving longer term IT problems of scaling and provisioning; while others use us as an immediate way to speed up their design workflows. We are still in the process of learning about the market.”

How can the on-demand cloud computing platform dramatically accelerate chip design workflows? According to Harn Hua Ng, one  immediate benefit is an almost instantaneous fulfillment of peak demand IT requirements, for example, a urgent request to do 100 synthesis builds to fix a problem due yesterday. Or if the problem cannot be fixed, at least the design team will find out in a day rather than potentially in three months’ worth of runtime without a cloud solution. The longer term acceleration is a gradual parallelization of the design workflow.

Currently, chip designers tend to visualize the design workflow as a chain of mostly serial steps with many dependencies, just because many steps can be time-consuming (both in terms of runtime and time taken to analyze intermediate results).

With an on-demand compute platform, designers can have more room to experiment and to optimize, more readily incorporating agile practices in hardware development.
Read more…

Lattice inaugurates new India office; to develop ECP5 products

April 4, 2011 Comments off

Lattice India GM, Sidhartha Mohanty and Lattice president and CEO, Darin G. Billerbeck at the opening of the India office.

Lattice India GM, Sidhartha Mohanty and Lattice president and CEO, Darin G. Billerbeck at the opening of the India office.

Today, Lattice Semiconductor Corp. announced the official inauguration of Lattice India in a ribbon cutting ceremony in Koramangala, Bangalore, that included Lattice president and CEO, Darin G. Billerbeck, and Lattice India GM, Sidhartha (Sid) Mohanty.

Billerbeck noted: “We build mostly custom built products, and in future, we would be building more low cost products. We are now restructuring the company. In fact, we just completed our strategic long-term roadmap (SLR).

He added: If you look at India, we develop low-cost applications over here. It also helps in giving us better communications with customers. It is now an option for India to do hardware design. Some of our products will stay on 65nm for a long time.”

In FPGAs, Lattice is strong on the ECP3 family, a third generation high value FPGA, which offers the industry’s lowest power consumption and price of any SERDES-capable FPGA device.

The LatticeECP3 FPGA family offers multi-protocol 3.2G SERDES with XAUI jitter compliance, DDR3 memory interfaces,

Inaugurating the Lattice India office in Bangalore.

Inaugurating the Lattice India office in Bangalore.

powerful DSP capabilities, high density on-chip memory and up to 149K LUTS, all with half the power consumption and half the price of competitive SERDES-capable FPGAs. The entire LatticeECP3 family is manufactured using Fujitsu’s advanced low power process technology.

Billerbeck noted that some of the ECP3 and ECP4 products will stay on the 65nm line. “ECP3 is already in production, while the ECP4 will be next. ECP5 family will come out in the next two years from now, and focus on 28nm.”

He noted: “We are not in an ‘arms race’ with the likes of Intel. Xilinx, etc. Our focus: We want to win in the low power. Our value proposition is in low power and communication spaces. We also want to be innovative.”

According to him, Altera had a great last year. Even Xilinx can bounce back. Lattice also has much more cash. It can do acquisitions now, if it so wishes. “People are now looking at new growth opportunities in smaller companies, so that’s a great opportunity. Our software team is very good. The guy in San Jose is very good.” Read more…

Semiconductor-IP directory for FPGAs indexes over 17,000 IP blocks and FPGA devices!

Today, I came across a very interesting story, which stated that Parallel Engines has launched the world’s largest semiconductor-IP directory for FPGAs. According to the company, the site —, indexes over 17,000 IP blocks and FPGA devices!

How does this help the global semiconductor industry? Most critically, customers can now search for semiconductor-IP and retrieve IP vendor datasheets, IP meta-information, and FPGA device configurations. Also, the meta-information includes IP interfaces, LUT, BRAM, I/O and embedded IP resources, costs and packages.

According to the release, Parallel Engines is the brainchild of its CEO, George Janac, Electronic Design Automation pioneer, founder of Chip Estimate; High Level Design Systems, and startup investor. “FPGA design has long been served by a disaggregated IP supply chain,” says Janac.

The next best thing to do was to get in touch with George Janac and have his thoughts.

First, I quizzed Janac about the need for such a site. He said that today, most IP portals are really the outgrowth of IPs for ASICs and SoCs.

Janac added: “The FPGA IP market really has no central IP place of its own. Also there is a unique need in FPGA to combine both IP and devices. Much of what is ASIC and SoC hard-IP (I/O, PHY, memory, PLL, etc.) is really embedded in an FPGA device. Hence, the need for a specialized portal. Also, many ASIC and SoC suppliers do not sell in FPGA and vice versa.” Very interesting indeed!

If this is the case, why develop such a site now, and why not earlier?

Janac explained: “Timing is driven by the sizes of the new generation of FPGAs, especially the recent announcements of the upcoming 28nm FPGA devices from Altera and Xilinx, respectively. These device will put the FPGA devices two to  three generations ahead in IC technology compared to ASIC. It means that more and more systems that were ASIC, could be placed in FPGA.

“Additionally, we are seeing more heterogeneous FPGA devices from companies like Actel. These have high embedded content for analog, and ARM cores. Finding this kind of IP and mapping to these devices needs a new approach.” Read more…

Altera expands low-cost Cyclone FPGA series

November 3, 2009 1 comment

Altera's Cyclone IV FPGA.Altera Corp. has introduced the Cyclone IV FPGAs, thereby expanding the success of the low-cost Cyclone series.

The Cyclone IV GX is said to be the lowest cost, lowest power FPGAs with transceivers, and the Cyclone IV E has helped it extend the lead in combining low cost, low power, and high functionality. Simultaneously, Altera also extended its transceiver portfolio leadership.

The Cyclone IV FPGA family offers two variants. Cyclone IV GX devices have up to 150K logic elements (LEs), up to 6.5-Mbits of RAM, up to 360 multipliers, and up to eight integrated 3.125-Gbps transceivers supporting mainstream protocols including Gigabit Ethernet (GbE), SDI, CPRI, V-by-One and Cyclone IV GX has hard IP for PCI Express (PCIe).

According to Jennifer Lo, Senior Marketing Manager, Altera, the company is pushing bandwidth limits in cost-sensitive markets and products — specifically, smartphones, wireless communications, industrial Ethernet, broadcast and 3D displays.

There is said to be a huge demand from Latin America, Asia, etc., specifically in wireless. Altera is providing a low cost, low power solution. Next, the trend is also moving from 2D to 3D displays. In broadcast it is moving to high bandwidth, in order to support HD video.

Easier for designers to debug FPGA designs
With the new Cyclone IV, will it become easier for designers to debug FPGA designs, especially when looking at the hardware and software aspects? Lo said that ease of use has always been a focus for low-end products for Altera.

“To that end, with Cyclone IV FPGA’s, like other Cyclone series, we strive to provide reference designs, design examples, development boards to customers to jump-start their design. With respect to debugging, we don’t see any particular differences between Cyclone IV and previous Cyclone generations.

“However, with more training, both fundamental trainings offered free on-line and more in-depth instructor-led trainings are available to help customers get accustomed with the Altera design methodology and use of our Industry-leading development software,” she added.

Altera had introduced the Cyclone III LS FPGA development kit, as well as shipments of industry’s first FPGAs with integrated 11.3-Gbps transceivers. How are all of these going to help Altera overall, given that Q3 saw a 3 percent increase; and help boost FPGA sales?

Lo added: “FPGAs usually have a longer design cycle (at least a few months before prototyping and another few months till mass production. With the recent few product additions, Altera is in a technology leadership position that we are all very proud of and confident that we will be able to reap the results of in the near future.” Read more…

Think AND not OR; Altera first @ 40nm FPGAs

May 19, 2008 Comments off

Altera has announced two new product lines — the Stratix IV FPGAs, which feature up to 680K logic elements, as well as the HardCopy IV ASICs, which has Gigabit transceivers embedded within the PLCs and allow seamless FPGA prototyping to hard core ASIC production.

Altera has also introduced the Quartus II software v8.0, which delivers unprecedented performance and productivity for FPGAs. It allows customers to assign power constraints on designs.

This is a global launch, and I feel proud to be associated with it. I am probably among the earliest to break this news to the world!

“All of these have been made possible due to Altera’s relationship with TSMC,” according to Gangatharan Gopal, country manager, India, Altera Semiconductor India Pvt. Ltd.

Altera’s 40nm devices are targeted at high-end applications such as wireless and wireline communications, military, broadcasting and ASIC prototyping.

The Statix IV FPGAs feature 680K logic elements, up to 22.4Mbits internal RAM, up to 48 transceiver blocks operating at up to 8.5Gbps, core performance of 350MHz, and hard IP for PCI Express Gen 1 and Gen 2.

The Stratix IV FPGAs are available in two majpr product groups — the GX devices or Gigabit Ethernet devices, which have up to 530K logic elements, and the E devices or enhanced Stratix IV, which support more memory per logic element. There are a total of eight devices per family.

The HardCopy ASICs IV feature seamless prototyping, so that customers can have the same RTL, same IP set and one tool, come with transceivers — similar transceiver block as the Stratix IV, offer lowest risk and lowest total cost access to deep sub-micron ASIC benefits, and provde 50x low power than companion FPGAs.

The HardCopy IV features 13.3 million gates. Gopal said: “Altera has surpassed the average industry ASIC density. We are now offering 13.3 million gates with HardCopy IV. With this, we can now address 80 percent of the market requirements.”

The HardCopy IV also comes in GX and E versions. Each version has six devices, supporting more memories and transceiver blocks.

Higher densities require higher levels of productivity
Altera’s Quartus II software v8.0 is specifically addressing this market need. It is said to be leading in productivity for high-end FPGAs and HardCopy ASICs. Features include TimeQuest — for timing analysis, Compilation Speed — via incremental compilation, PowerPlay technology — which allows power management; and SOPC Builder — which facilitates system-level design.

Altera is addressing the issue of compile times at three fronts — algorithms, multiprocessor support and incremental compile support. The Quartus II v8.0 is said to deliver 20 percent average annual compile time improvement.

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