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FinFETs delivering on promise of power reduction: Synopsys

February 1, 2014 Comments off

Here is the concluding part of my conversation with Synopsys’ Rich Goldman on the global semiconductor industry.

Rich Goldman

Rich Goldman

Global semicon in sub 20nm era
How is the global semicon industry performing after entering the sub 20nm era? Rich Goldman, VP, corporate marketing and strategic alliances, Synopsys, said that driving the fastest pace of change in the history of mankind is not for the faint of heart. Keeping up with Moore’s Law has always required significant investment and ingenuity.

“The sub-20nm era brings additional challenges in device structures (namely FinFETs), materials and methodologies. As costs rise, a dwindling number of semiconductor companies can afford to build fabs at the leading edge. Those thriving include foundries, which spread capital expenses over the revenue from many customers, and fabless companies, which leverage foundries’ capital investment rather than risking their own. Thriving, leading-edge IDMs are now the exception.

“Semiconductor companies focused on mobile and the Internet of Things are also thriving as their market quickly expands. Semiconductor companies who dominate their space in such segments as automotive, mil/aero and medical are also doing quite well, while non-leaders find rough waters.”

Performance of FinFETs
Have FinFETs gone to below 20nm? Also, are those looking for power reduction now benefiting?

He added that 20nm was a pivotal point in advanced process development. The 20nm process node’s new set of challenges, including double patterning and very leaky transistors due to short channel effects, negated the benefits of transistor scaling.

To further complicate matters, the migration from 28nm to 20nm lacked the performance and area gains seen with prior generations, making it economically questionable. While planar FET may be nearing the end of its scalable lifespan at 20nm, FinFETs provide a viable alternative for advanced processes at emerging nodes.

The industry’s experience with 20nm paved the way for an easier FinFET transition. FinFET processes are in production today, and many IC design companies are rapidly moving to manufacture their devices on the emerging 16nm and 14nm FinFET-based process geometries due to the compelling power and performance benefits. Numerous test chips have taped out, and results are coming in.

“FinFET is delivering on its promise of power reduction. With 20nm planar FET technologies, leakage current can flow across the channel between the source and the drain, making it very difficult to completely turn the transistor off. FinFETs provide better channel control, allowing very little current to leak when the device is in the “off” state. This enables the use of lower threshold voltages, resulting in better power and performance. FinFET devices also operate at a lower nominal voltage supply, significantly improving dynamic power.”
Read more…

Atrenta on outlook for EDA in 2014

January 14, 2014 1 comment

I had interacted with Dr. Ajoy Bose, CEO of Atrenta, some months ago. It was a pleasure to meet up with Piyush Sancheti, VP of Marketing recently. First, I asked him about the outlook for EDA in 2014.

Piyush Sancheti

Piyush Sancheti

Outlook for EDA
Piyush Sancheti said: “EDA does not look that attractive from growth point. However, you cannot do SoC designs without EDA. Right now, EDA’s focus is on implementation. The re-use of IP has been doing the rounds for many years. Drivers for SoCs are mobile and Internet of Things. The design cycle for those markets are very short – about three months. EDA business is shifting to IP re-use. The focus is now toward design aggregation.

“We will have done roughly 66 percent of business – net new — on existing customers. There is an industry shift toward doing more on the front end. EDA growth will come from IP-SoC involvement.

“Sub-20nm has challenges. ST says FT-SoI is the way to go. Complexity of process plays a big role, and the amount of chips you put in will also increase. In 14/16nm, we have an investment going on in 3D design. We are extending our 2D tool into 3D tool. We are also investing in the IP qualification. We have standardized a set of design rules in RTL. There are about 30 companies in the TSMC ecosystem.

“Our main focus is IP enablement. SoC acceptance is another key aspect. Our company focus is IP-enablement for SoCs. IP qualification ensures that it meets guidelines. Second, acceptance and making sure all IPs fit in the blocks. Third, integration. We already have this technology and it is driving the business.”

3D design
What’s Atrenta’s take on 3D design? Sancheti replied: “The industry has been slow as 3D designs are not yet to a point of business success. Focus on monolithic 3D-ICs will be a paradigm shift for the semicon industry. For mainstream commercial design, 20nm is still mainstream, but 14/16nm does not look mainstream, as of now. Process node is not necessarily a driver of innovation. EDA as an industry will remain in single digit growth.”

How will EDA move into the embedded software space?

Sancheti said: “We’ve looked into that market. But, the price point is significantly lower. Over time, it could be a strategic area for us. Over time, embedded software development and chip design will co-mingle.”

ESL is where the future of EDA lies. Still true? He added that the future of EDA is going up. It has to head toward integration of embedded software and chip development. However, ESL is not the only viable option.

Atrenta has 220 people in India, about 10 people in Bangalore and 200 in Noida. Sushil Gupta runs the India operations. It has tie-ups with IIT Delhi and IIT Kharagpur as well. Atrenta sees lot of scope for work with the Indian start-ups.

Round-up 2013: Best of semiconductors, electronics and solar

December 31, 2013 Comments off

Virtex UltraScale device.

Virtex UltraScale device.

Friends, here’s a review of 2013! There have been the usual hits and misses, globally, while in India, the electronics and semiconductor industries really need to do a lot more! Enjoy, and here’s wishing everyone a Very Happy and Prosperous 2014! Be safe and stay safe!!

DEC. 2013
What does it take to create Silicon Valley!

How’s global semicon industry performing in sub-20nm era?

Xilinx announces 20nm All Programmable UltraSCALE portfolio

Dr. Wally Rhines: Watch out for 14/16nm technologies in 2014!

Outlook 2014: Xilinx bets big on 28nm

NOV. 2013
Indian electronics scenario still dull: Leaptech

Connecting intelligence today for connected world: ARM

India poses huge opportunity for DLP: TI

SEMICON Europa 2013: Where does Europe stand in 450mm path?

OCT. 2013
Apple’s done it again, wth iPad Air!

IEF 2013: New markets and opportunities in sub-20nm era!

SEPT. 2013
ST intros STM32F4 series high-performance Cortex-M4 MCUs

Great, India’s having fabs! But, is the tech choice right?

G450C

G450C

Now, India to have two semicon fabs!

Higher levels of abstraction growth area for EDA

AUG. 2013
Moore’s Law could come to an end within next decade: POET

What’s happening with 450mm: G450C update and status

300mm is the new 200mm!

JULY 2013
Xilinx tapes-out first UltraScale ASIC-class programmable architecture

JUNE 2013
EC’s goal: Reach 20 percent share in chip manufacturing by 2020!
Read more…

IEF 2013: New markets and opportunities in sub-20nm era!

October 15, 2013 1 comment

Future Horizons hosted the 22nd Annual International Electronics Forum, in association with IDA Ireland, on Oct. 2-4, 2013, at Dublin, Blanchardstown, Ireland. The forum was titled ‘New Markets and Opportunities in the Sub-20nm Era: Business as Usual OR It’s Different This Time.” Here are excerpts from some of the sessions. Those desirous of finding out much more should contact Malcolm Penn, CEO, Future Horizons.

Liam BritnellLiam Britnell, European manager and Research Scientist, Bluestone Global Tech (BGT) Materials spoke on Beyond Graphene: Heterostructures and Other Two-Dimensional Materials.

The global interest in graphene research has facilitated our understanding of this rather unique material. However, the transition from the laboratory to factory has hit some challenging obstacles. In this talk I will review the current state of graphene research, focusing on the techniques which allow large scale production.

I will then discuss various aspects of our research which is based on more complex structures beyond graphene. Firstly, hexagonal boron nitride can be used as a thin dielectric material where electrons can tunnel through. Secondly, graphene-boron nitride stacks can be used as tunnelling transistor devices with promising characteristics. The same devices show interesting physics, for example, negative differential conductivity can be found at higher biases. Finally, graphene stacked with thin semiconducting layers which show promising results in photodetection.

I will conclude by speculating the fields where graphene may realistically find applications and discuss the role of the National Graphene Institute in commercializing graphene.

Jean-Rene Lequepeys, VP Silicon Components, CEA-Leti, spoke on  Advanced Semiconductor Technologies Enabling High-Performance Jean-Rene Lequepeysand Energy Efficient Computing.

The key challenge for future high-end computing chips is energy efficiency in addition to traditional challenges such as yield/cost, static power, data transfer. In 2020, in order to maintain at an acceptable level the overall power consumption of all the computing systems, a gain in term of power efficiency of 1000 will be required.

To reach this objective, we need to work not only at process and technology level, but to propose disruptive multi-processor SoC architecture and to make some major evolutions on software and on the development of
applications. Some key semiconductor technologies will definitely play a key role such as: low power CMOS technologies, 3D stacking, silicon photonics and embedded non-volatile memory.

To reach this goal, the involvement of semiconductor industries will be necessary and a new ecosystem has to be put in place for establishing stronger partnerships between the semiconductor industry (IDM, foundry), IP provider, EDA provider, design house, systems and software industries.

Andile NgcabaAndile Ngcaba, CEO, Convergence Partners, spoke on Semiconductor’s Power and Africa – An African Perspective.

This presentation looks at the development of the semiconductor and electronics industries from an African perspective, both globally and in Africa. Understanding the challenges that are associated with the wide scale adoption of new electronics in the African continent.

Electronics have taken over the world, and it is unthinkable in today’s modern life to operate without utilising some form of electronics on a daily basis. Similarly, in Africa the development and adoption of electronics and utilisation of semiconductors have grown exponentially. This growth on the African continent was due to the rapid uptake of mobile communications. However, this has placed in stark relief the challenges facing increased adoption of electronics in Africa, namely power consumption.

This background is central to the thesis that the industry needs to look at addressing the twin challenges of low powered and low cost devices. In Africa there are limits to the ability to frequently and consistently charge or keep electronics connected to a reliable electricity grid. Therefore, the current advances in electronics has resulted in the power industry being the biggest beneficiary of the growth in the adoption of electronics.

What needs to be done is for the industry to support and foster research on this subject in Africa, working as a global community. The challenge is creating electronics that meet these cost and power challenges. Importantly, the solution needs to be driven by the semiconductor industry not the power industry. Focus is to be placed on operating in an off-grid environment and building sustainable solutions to the continued challenge of the absence of reliable and available power.

It is my contention that Africa, as it has done with the mobile communications industry and adoption of LED lighting, will leapfrog in terms of developing and adopting low powered and cost effective electronics.

Jo De Boeck, senior VP and CTO, IMEC, discussed Game-Changing Technology Roadmaps For Lifescience. Jo De Boeck

Personalized, preventive, predictive and participatory healthcare is on the horizon. Many nano-electronics research groups have entered the quest for more efficient health care in their mission statement. Electronic systems are proposed to assist in ambulatory monitoring of socalled ‘markers’ for wellness and health.

New life science tools deliver the prospect of personal diagnostics and therapy in e.g., the cardiac, neurological and oncology field. Early diagnose, detailed and fast screening technology and companioning devices to deliver the evidence of therapy effectiveness could indeed stir a – desperately needed – healthcare revolution. This talk addresses the exciting trends in ‘PPPP’ health care and relates them to an innovation roadmap in process technology, electronic circuits and system concepts.
Read more…

Dr. Wally Rhines on global semiconductor industry trends for 2013


It is always a pleasure speaking with Dr. Walden (Wally) C. Rhines, chairman and CEO, Mentor Graphics Corp. I met him on the sidelines of the 13th Global Electronics Summit, held at the Chaminade Resort & Spa, Santa Cruz, USA.

Status of global EDA industry

Dr. Wally Rhines.

Dr. Wally Rhines.

First, I asked Dr. Rhines how the EDA industry was doing. Dr. Rhines said: “The global EDA industry has been doing pretty well. The results have been pretty good for 2012. In general, the EDA industry tends to follow the semiconductor R&D by at least 18 months.”

For the record, the electronic design automation (EDA) industry revenue increased 4.6 percent for Q4 2012 to $1,779.1 million, compared to $1,700.1 million in Q4 2011.

Every region, barring Japan, grew in 2012. The Asia Pacific rim grew the fastest – about 12.5 percent. The Americas was the second fastest region in terms of growth at 7.4 percent, and Europe grew at 6.8 percent. However, Japan decreased by 3 percent in 2012.

In 2012, the segments that have grown the fastest within the EDA industry include PCB design and IP, respectively. The front-end CAE (computer aided engineering) group grew faster than the backend CAE. By product category, CAE grew 9.8 percent. The overall growth for license and maintenance was 7 percent. Among the CAE areas, design entry grew 36 percent and emulation 24 percent, respectively.

DFM also grew 28 percent last year. Overall, PCB grew 7.6 percent, while PCB analysis was 25 percent. IP grew 12.6 percent, while the verification IP grew 60 percent. Formal verification and power analysis grew 16 percent each, respectively. “That’s actually a little faster than how semiconductor R&D is growing,” added Dr. Rhines.

Status of global semicon industry
On the fortunes of the global semiconductor industry. Dr. Rhines said: “The global semiconductor industry grew very slowly in 2012. Year 2013 should be better. Revenue was actually consolidated by a lot of consolidations in the wireless industry.”

According to him, smartphones should see further growth. “There are big investments in capacities in the 28nm segment. Folks will likely redesign their products over the next few years,” he said. “A lot of firms are waiting for FinFET to go to 20nm. People who need it for power reduction should benefit.”

“A lot of people are concerned about Japan. We believe that Japan can recover due to the Yen,” he added.
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Synopsys on outlook for global semicon 2013!

January 17, 2013 1 comment

Thanks to Sheryl Gulizia, senior manager, Worldwide Public Relations, Synopsys Inc., I was able to connect with John Chilton, senior VP of Marketing and Strategic Development, Synopsys. We discussed the global (and Indian) outlook for the semiconductor industry in detail. Dr. Aart De Geus was apparently away on a business meet. 

John Chilton.

John Chilton.

According to Chilton, the semiconductor industry has repeatedly stared down the daunting technical challenges caused by the necessity of Moore’s Law and the inevitability of the laws of physics. Every time, the industry has risen to the challenge and delivered silicon that is smaller, faster and cheaper, and the design and systems companies that were quickest to exploit the new technologies reaped the great benefit.

Power dissipation challenging
One trend that has proven to be especially challenging is power dissipation. Although transistors get smaller, faster and cheaper, chip power keeps increasing. Increasing power and decreasing size could have caused device-melting energy densities, but the industry rose to the challenge with more innovative physics along with smarter design methods and tools.

This time around, the challenge seems more fundamental, with the new nodes offering either better performance or lower power, but not both at the same time, and maybe not at a lower cost. The fundamental driving factor behind innovation has been smaller, faster and cheaper transistors, with the cheaper part making the migration a no-brainer. Unfortunately, this time the new node is not expected to be cheaper.

App processors to drive move to 20nm
Application processors for mobile and cloud-based services will drive the move to 20nm. These applications have the volume and power/performance needs to justify the expected investment required to embrace the 20nm node. Recent product announcements at CES underscore the emergence of the ‘cloud to mobile client’ trend in consumer electronics.

Dell and Wyse unveiled the project Ophelia. Ophelia is a USB memory stick-sized thin client that will plug into any compatible TV or Dell monitor. The device will boot into an Android OS and turn any TV into a portal to access a computer somewhere else. Ophelia works by taking advantage of the MHL protocol and works with any MHL-enabled display. Over 100-million MHL-compliant chipsets have already been shipped, so the opportunities for this type of interaction are growing.

MHL, along with established standards such as USB and HDMI or even future short-range wireless standards, will enable consumers to plug their cell phone into any monitor or TV and consume content via their phone on a larger, more satisfying display.

Coincidentally, on the same day, Samsung announced consumer displays that utilize voice and gesture recognition. These emerging technologies will begin to redefine the way we interact with the cloud. Instead of carrying a laptop, you may end up waving and talking to a TV. In a futuristic presentation, Lexus showed a prototype of a laser-scanning system that is small enough to be mounted on a grill and makes 3-D maps of the environment surrounding a car. This kind of embedded vision technology will make its way into more devices as processor performance increases.

Chilton said that developing such complex systems and applications require a robust verification solution. Chip designers already use complex and exhaustive test benches to test individual blocks and subsystems. Verification engineers will need to move up to the next level and handle the full verification of the SoC within a target system.

Verification of an integrated system will require an integrated verification solution that includes not just simulation but also acceleration, emulation and formal debug. A new, integrated verification platform should combine these existing discrete technologies to offer the productivity needed to realize complex systems with predictable, manageable schedules.

Delivering the hardware simultaneously with a working OS and development kit will require virtual prototypes, which will be used by software developers prior to the release of working hardware.
Read more…

Focus on good power-aware verification strategy for SoCs: Dr. Wally Rhines

January 7, 2013 1 comment

Dr. Wally Rhines.

Dr. Wally Rhines.

It is always a pleasure to chat with Dr. Wally (Walden C.) Rhines, chairman and CEO, of Mentor Graphics. I chatted with him, trying to understand gigascale design, verification trends, strategy for power-aware verification, SERDES design challenges, migrating to 3D FinFET transistors, and Moore’s Law getting to be “Moore Stress”!

Chip design in gigascale, hertz, complex
First, I asked him to elaborate on how implementation of chip design will evolve, with respect to gigascale design, gigahertz and gigacomplex geometries.

He said: “Thanks to close co-operation among members of the foundry ecosystem, as well as cooperation between IDMs and their suppliers, serious development of design methods and software tools is running two to three generations ahead of volume manufacturing capability. For most applications, “Gigascale” power dissipation is a bigger challenge than managing the complexity but “system-level” power optimization tools will continue to allow rapid progress. Thermal analysis is becoming part of the designer’s toolkit.”

Functional verification is continually challenged by complexity but there have been, and continue to be, many orders of magnitude improvement in performance just from adoption of emulation, intelligent test benches and formal methods so this will not be a major limitation.

The complexity of new physical design problems will, however, be very challenging. Design problems ranging from basic ESD analysis, made more complex due to multiple power domains, to EMI, electromigration and intra-die variability are now being addressed with new design approaches. Fortunately, programmable electrical rule checking is being widely adopted and will help to minimize the impact of these physical effects.

Is verification keeping up?
How is the innovation in verification keeping up with trends?

Dr. Rhines added that over the past decade, microprocessor clock speeds have leveled out at 3 to 4 GHz and server performance improvement has come mostly from multi-core architectures. Although some innovative approaches have allowed simulators to gain some advantage from multi-core architectures, the speed of simulators hasn’t kept up with the growing complexity of leading edge chips.

Emulators have more than made up the difference. Emulators offer more than four orders of magnitude faster performance than simulators and emulators do so at about 0.005X the cost per cycle of simulation. The cost of power per year is more than one third the cost of hardware in a large simulation farm today, while emulation offers a 12X savings in power per verification clock cycle. For those who design really complex chips, a combination of emulation and simulation, along with formal methods and intelligent test benches, has become standard.

At the block and subsystem level, high level synthesis is enabling the next move up in design and verification abstraction. Since verification complexity grows at about the square of component count, we have plenty of room to handle larger chips by taking advantage of the four orders of magnitude improvement through emulation plus another three or four orders of magnitude through formal verification techniques, two to three orders of magnitude from intelligent test benches and three orders of magnitude from higher levels of abstraction.

By applying multiple engines and multiple abstraction levels to the challenge of verifying chips, the pressure is on to integrate the flow. Easily transitioning and reusing verification efforts from every level—including tests and coverage models, from high level models to RTL and from simulation to emulation—is being enabled through more powerful and adaptable verification IP and high level, graph-based test specification capabilities. These are keys to driving verification reuse to match the level of design reuse.

Powerful verification management solutions enable the collection of coverage information from all engines and abstraction levels, tracking progress against functional specifications and verification plans. Combining verification cycle productivity growth from emulation, formal, simulation and intelligent testing with higher verification abstraction, re-use and process management provides a path forward to economically verifying even the largest, most complex chips on time and within budget.

Good power-aware verification strategy for SoCs
What should be a good power-aware verification strategy for SoCs

According to him, the most important guideline is to start power-aware design at the highest possible level of system description. The opportunity to reduce system power is typically an order of magnitude greater at the system level than at the RTL level. For most chips today, that means at least the transaction level when the design is still described in C++ or SystemC.

Significant experience and effort should then be invested at the RTL level using synthesis and UPF-enabled simulation. Verification solutions typically automate the generation of correctness checks for power-control sequences and power-state coverage metrics. As SoC power is typically managed by software, the value of a hardware/software co-verification and co-debug solution in simulation and emulation becomes apparent in power-management verification at this level.

As designers proceed to the gate and transistor level, accuracy of power estimation improves. That is why gate level analysis and verification of the fully implemented power management architecture is important. Finally, at the physical layout, designers traditionally were stuck with whatever power budget was passed down to them. Now,they increasingly have power goals that can be achieved using dozens of physical design techniques that are built into the place and route tools.
Read more…

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