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SuVolta solving power problem in SoCs across multiple CMOS process nodes

December 7, 2011 6 comments

SuVolta Inc., based in California, USA, develops and licenses CMOS semiconductor technologies that significantly reduce the power consumption of integrated circuits (ICs). Back in June 2011, introduced the PowerShrink low-power platform and the first licensee, Fujitsu. Thanks to Amanda Crnkovich of The Hoffmann Agency, I interacted with Dr. Scott E. Thompson, CTO, SuVolta, on the deeply depleted channel (DDC) technology that delivers over 50 percent reduction in IC power consumption, while maintaining performance.

Dr. Scott E. Thompson, CTO, SuVolta.

Dr. Scott E. Thompson, CTO, SuVolta.

What’s DDC technology all about?
First, I asked Dr. Thompson what the DDC technology is all about? He said that SuVolta’s PowerShrink platform in planar, bulk CMOS provides dramatic improvements in variability and device performance, and is compatible with existing CMOS processes. It integrates using conventional fabrication equipment and materials, and enables the reuse of existing circuit IP infrastructure. SuVolta is focusing on solving the power problem in system-on-chips (SoCs) across multiple CMOS process technology nodes.

He added: “SuVolta’s DDC transistor reduces threshold voltage (VT) variability and enables continued CMOS scaling. The structure works by forming a deeply depleted channel when a voltage is applied to the gate. In a typical implementation the DDC channel has several regions – an undoped or very lightly doped region, a VT setting offset region and a screening region. Each implementation of SuVolta’s DDC transistor may vary depending on the wafer fabrication facility and specific chip design requirements.”

The DDC transistor has a much tighter distribution of threshold voltages. In addition, DDC transistors allow for the setting of multiple VTs, which is vital for today’s low-power products.

“Perhaps, the biggest benefit is in embedded SRAM memory blocks. For most chips, lowering supply voltage is limited by the SRAM. However, with a DDC transistor, conventional 6T SRAMs have been demonstrated operating below 500 milli Volts. This is significant as it is amongst the lowest voltage ever reported in a standard embedded SRAM,” added Dr. Thompson.

Impact on reducing IC power consumption in devices
So, what impact will all of this have on reducing IC power consumption in devices, such as smartphones, tablets, etc.? While the increased density in transistors enables more features for all types of devices, power has now become the biggest issue in semiconductors. This “power impasse” is critical or two reasons:

* Excessive power consumption limits battery life for mobile devices, and causes huge electricity bills for server farms.
* Devices are hitting their thermal (heat) limit, thus preventing more capabilities from being added. Power consumption directly creates heat. This is becoming a major problem in mobile devices, which have very strict thermal limits. To hit thermal limits, chip makers must forego adding additional content, or “throttle” the chip back to a slower speed.

The impact of excess power on consumers is profound: shorter battery life, lower-content mobile devices – fewer features and/or slower performance, higher electronics costs because transistors hit their scaling limit because of power, excessive energy bills and an increased global demand for energy.

Dr. Thompson added: “SuVolta’s PowerShrink platform enables semiconductor firms to cut chip power in half without sacrificing performance, losing functionality, or migrating to a more advanced, and costly, semiconductor process node. And, it does so using planar, bulk CMOS, and does not require development of new manufacturing facilities or IP blocks.” Read more…

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