Archive for the ‘hardware/software co-verification’ Category

Round-up 2013: Best of semiconductors, electronics and solar

December 31, 2013 Comments off

Virtex UltraScale device.

Virtex UltraScale device.

Friends, here’s a review of 2013! There have been the usual hits and misses, globally, while in India, the electronics and semiconductor industries really need to do a lot more! Enjoy, and here’s wishing everyone a Very Happy and Prosperous 2014! Be safe and stay safe!!

DEC. 2013
What does it take to create Silicon Valley!

How’s global semicon industry performing in sub-20nm era?

Xilinx announces 20nm All Programmable UltraSCALE portfolio

Dr. Wally Rhines: Watch out for 14/16nm technologies in 2014!

Outlook 2014: Xilinx bets big on 28nm

NOV. 2013
Indian electronics scenario still dull: Leaptech

Connecting intelligence today for connected world: ARM

India poses huge opportunity for DLP: TI

SEMICON Europa 2013: Where does Europe stand in 450mm path?

OCT. 2013
Apple’s done it again, wth iPad Air!

IEF 2013: New markets and opportunities in sub-20nm era!

SEPT. 2013
ST intros STM32F4 series high-performance Cortex-M4 MCUs

Great, India’s having fabs! But, is the tech choice right?



Now, India to have two semicon fabs!

Higher levels of abstraction growth area for EDA

AUG. 2013
Moore’s Law could come to an end within next decade: POET

What’s happening with 450mm: G450C update and status

300mm is the new 200mm!

JULY 2013
Xilinx tapes-out first UltraScale ASIC-class programmable architecture

JUNE 2013
EC’s goal: Reach 20 percent share in chip manufacturing by 2020!
Read more…

Zebu-Server — Enterprise-type emulator from EVE

Friends, this is a guest post by Ms Usha Prasad, Associate Partner, PC Mediaworks. May I take this opportunity to welcome you to my blog, Usha!

Recently, EVE had launched the ZeBu-Server. Let us find out more about it!

EVE Design Automation Ltd., a leader in hardware/software co-verification, has ushered in a new era of hardware-assisted verification with the launch of the ZeBu-Server, a scalable emulation system capable of handling up to one-billion ASIC gates.

The ZeBu-Server is housed in a compact chassis with a small footprint and sets a new standard for small size, light weight and low power consumption making it an environment friendly emulator.

Addressing needs of current, future ASIC/SoC verification
EVE launched ZeBu-Server at a time when the entire industry is quite silent about launching new products. Driven by market demand, EVE, with its strong R&D capabilities rolled out the ZeBu-Server to address the needs of current and future ASIC/SoC verification.

With designs getting larger, growth in embedded software content, verification sequences getting longer and more complex, there is a need for emulation products with higher capacity, higher performance and smarter debugging features. Covering all of these aspects, EVE has chalked out a clear cut R&D roadmap with the ZeBu-Server’s launch.

This particular solution is EVE’s next generation emulation box, based on V-5 LX330 FPGAs, with a total design capacity of one billion ASIC-equivalent gates. It is scalable from 10 million gates in increments of 10-, 20-, and 40-million gates.

Providing details on the ZeBu-Server, Montu Makadia, EVE’s director and country sales manager, India, said: “It is a completely new emulator with many new features and capabilities, such as multi-user, relocation capability and multi-RTB (reconfigurable test bench) that increases the data transfer rate in transaction mode to 5 million transactions per second.”

Multi-core capabilities
Zebu-Server has multi-core capabilities as well! “A brand new compiler based on multi-core technology has been specifically architected for large, multi-core designs, and it provides fast incremental and parallel compilation. Zebu-Server can map designs of 50+ million gates at a rate of 30 million gates per hour on a farm of PCs. But very large (hundreds of millions of gates) multi-core designs can be mapped at 100 million gates per hours,” he added.

“The multi-core feature breaks the design compilation into multiple sub-blocks, and enables the process to be parallelized, and run on a PC farm. It supports module-based scalability. The system is comprised of multiple units and each unit can be configured with up to five modules for a total capacity of 200M ASIC gates. A fully configured system includes five units (25 modules),” he explained.

Smart debugging capabilities
The other important highlight of the ZeBu-Server is its smart debugging capabilities such as SystemVerilog Assertion support and run-time access to every register and signal in the design.

It can map designs of 50+ million gates at a rate of 30 million gates per hour on a farm of PCs. However, very large multi-core designs can be mapped at 100 million gates per hours, as mentioned earlier.

Potential users of ZeBu-Server
Naturally, it would be apt to determine who would be the potential users of ZeBu-Server.

Not a surprise really, that actually, that eight out of the top 10 semiconductor companies are using ZeBu. “We not only see newer applications on processors and graphic chips to be emulated, but also see our existing clients scaling up on their designs. These are the key benefits for them while looking to migration with better speed performance that no traditional emulator can give with such larger design capacity that the ZeBu-Server can handle,” Makadia said.

New users will be benefited from ZeBu-Server’s exceptional capacity with the advantage of ZeBu’s high performance. “ZeBu is superior to that of any traditional emulator,” he contended.

Powerful design debugging
ZeBu-Server also helps in powerful design debugging. According to Makadia, ZeBu follows the FPGA flow. Having a very strong software is a key patent EVE enjoys, thus offering very smooth and powerful debugging features. “As per our experience, along with speed-through transactors, it is equally important to have good debugging.”

Elaborating further, Makadia said: “Our software helps clients to debug their designs with key features like at-speed static probes, trace memory and logic analyzer triggers to capture signals. However, beyond this, the ZeBu-Server also provides pre-compiled, high-speed flexible probes, which can be used to trace signals directly on to a hard disk, thus giving the user a virtually unlimited trace window.

“Support for SystemVerilog assertions makes it easier to isolate bugs during billions of cycles of emulation. Our enhanced dynamic probes provide the user with run-time access to any register, memory or signal in the design, without recompilation, which enables detailed design debug.”

Results a combo of test labs and actual users
It would be interesting to know whether the results are from the test labs or actual users.

The features in Zebu-Server has been embedded with results from test labs and actual users. According to Makadia, it is an enhancement of the features of EVE’s existing XXL box and software. XXL is very stable and used widely by most of EVE’s clients.

EVE has tested equally larger and complex designs that will run much faster on Server additionally, with its new Z-Fast Synthesis tool locked with Zebu compiler flow and faster Flexi probes to debug designs while verifying. “These features will surely help customers in a much better and faster way for larger designs,” he said.

Current ZeBu customers are already using EVE’s fast synthesis tool, zFAST, which is shown to perform 10x faster than third-party synthesis tools, and greatly improving the compilation time. The debug technology is already in use with the XXL, and has been verified in production.

Future enhancements on EVE’s roadmap include very fast design loading of few seconds regardless of the design size.

Key features of Zebu-Server
* Lowest cost-of-ownership.
* Leveraging the largest design capacity.
* Fastest compilation speed on designs exceeding 50 million ASIC-equivalent gates.
* Fastest execution speed.
* Multiple concurrent users.
* Most powerful design debugging.
* Most cycles per dollar in the industry.

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