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IEF 2013: New markets and opportunities in sub-20nm era!

October 15, 2013 1 comment

Future Horizons hosted the 22nd Annual International Electronics Forum, in association with IDA Ireland, on Oct. 2-4, 2013, at Dublin, Blanchardstown, Ireland. The forum was titled ‘New Markets and Opportunities in the Sub-20nm Era: Business as Usual OR It’s Different This Time.” Here are excerpts from some of the sessions. Those desirous of finding out much more should contact Malcolm Penn, CEO, Future Horizons.

Liam BritnellLiam Britnell, European manager and Research Scientist, Bluestone Global Tech (BGT) Materials spoke on Beyond Graphene: Heterostructures and Other Two-Dimensional Materials.

The global interest in graphene research has facilitated our understanding of this rather unique material. However, the transition from the laboratory to factory has hit some challenging obstacles. In this talk I will review the current state of graphene research, focusing on the techniques which allow large scale production.

I will then discuss various aspects of our research which is based on more complex structures beyond graphene. Firstly, hexagonal boron nitride can be used as a thin dielectric material where electrons can tunnel through. Secondly, graphene-boron nitride stacks can be used as tunnelling transistor devices with promising characteristics. The same devices show interesting physics, for example, negative differential conductivity can be found at higher biases. Finally, graphene stacked with thin semiconducting layers which show promising results in photodetection.

I will conclude by speculating the fields where graphene may realistically find applications and discuss the role of the National Graphene Institute in commercializing graphene.

Jean-Rene Lequepeys, VP Silicon Components, CEA-Leti, spoke on  Advanced Semiconductor Technologies Enabling High-Performance Jean-Rene Lequepeysand Energy Efficient Computing.

The key challenge for future high-end computing chips is energy efficiency in addition to traditional challenges such as yield/cost, static power, data transfer. In 2020, in order to maintain at an acceptable level the overall power consumption of all the computing systems, a gain in term of power efficiency of 1000 will be required.

To reach this objective, we need to work not only at process and technology level, but to propose disruptive multi-processor SoC architecture and to make some major evolutions on software and on the development of
applications. Some key semiconductor technologies will definitely play a key role such as: low power CMOS technologies, 3D stacking, silicon photonics and embedded non-volatile memory.

To reach this goal, the involvement of semiconductor industries will be necessary and a new ecosystem has to be put in place for establishing stronger partnerships between the semiconductor industry (IDM, foundry), IP provider, EDA provider, design house, systems and software industries.

Andile NgcabaAndile Ngcaba, CEO, Convergence Partners, spoke on Semiconductor’s Power and Africa – An African Perspective.

This presentation looks at the development of the semiconductor and electronics industries from an African perspective, both globally and in Africa. Understanding the challenges that are associated with the wide scale adoption of new electronics in the African continent.

Electronics have taken over the world, and it is unthinkable in today’s modern life to operate without utilising some form of electronics on a daily basis. Similarly, in Africa the development and adoption of electronics and utilisation of semiconductors have grown exponentially. This growth on the African continent was due to the rapid uptake of mobile communications. However, this has placed in stark relief the challenges facing increased adoption of electronics in Africa, namely power consumption.

This background is central to the thesis that the industry needs to look at addressing the twin challenges of low powered and low cost devices. In Africa there are limits to the ability to frequently and consistently charge or keep electronics connected to a reliable electricity grid. Therefore, the current advances in electronics has resulted in the power industry being the biggest beneficiary of the growth in the adoption of electronics.

What needs to be done is for the industry to support and foster research on this subject in Africa, working as a global community. The challenge is creating electronics that meet these cost and power challenges. Importantly, the solution needs to be driven by the semiconductor industry not the power industry. Focus is to be placed on operating in an off-grid environment and building sustainable solutions to the continued challenge of the absence of reliable and available power.

It is my contention that Africa, as it has done with the mobile communications industry and adoption of LED lighting, will leapfrog in terms of developing and adopting low powered and cost effective electronics.

Jo De Boeck, senior VP and CTO, IMEC, discussed Game-Changing Technology Roadmaps For Lifescience. Jo De Boeck

Personalized, preventive, predictive and participatory healthcare is on the horizon. Many nano-electronics research groups have entered the quest for more efficient health care in their mission statement. Electronic systems are proposed to assist in ambulatory monitoring of socalled ‘markers’ for wellness and health.

New life science tools deliver the prospect of personal diagnostics and therapy in e.g., the cardiac, neurological and oncology field. Early diagnose, detailed and fast screening technology and companioning devices to deliver the evidence of therapy effectiveness could indeed stir a – desperately needed – healthcare revolution. This talk addresses the exciting trends in ‘PPPP’ health care and relates them to an innovation roadmap in process technology, electronic circuits and system concepts.
Read more…

EDA Tech Forum 2010: Nanoscale regime and social product innovation!

August 18, 2010 Comments off

This a continuation of my coverage of the Mentor Graphics’ EDA Tech Forum 2010.

Here, I shall discuss the main points of the two keynotes by Dr. Kota Murali, lead scientist & program manager of nanotech, IBM India, and Manjunatha Hebbar, VP & Head – Strategic Services, HCL Technologies Ltd — my good friend and fellow board member at the Indian Microelectronics Academy (IMA).

Nanotech for a smarter planet

Dr. Kota Murali, lead scientist & program manager of nanotech, IBM India.

Dr. Kota Murali, lead scientist & program manager of nanotech, IBM India @ EDA Tech Forum 2010.

Dr. Kota Murali, lead scientist & program manager of nanotech, IBM India, presented on nanotech for a smarter planet. The motivation for nanotech at IBM has been — since IT has grown as devices have shrunk. Now, we have reached the nanoscale level. The challenge is: how do we take new technologies to markets?

He briefly touched upon IBM’s latest generation processor, the Power7, built on 45nm. The next generation Power8 processors are supposed to be built on 22nm/32nm.

He said that physical and chemical properties of materials depend on the size. Hence, it is important to use nano and quantum scale properties for next generation devices. There is this classical scaling reality — to maintain generational performance gains, supply voltage is not scaled ideally, leading to major power issues.

In the future, innovation, scaling and power will drive performance. Power will play a critical role in developing next-generation products.

On the novel high-K metal gate (HKMG) devices, these gates are already four monolayers thick. We need HKMG since it significantly reduces gate leakage and chips consume lesser power. Also, it allows equivalent oxide thickness. The shrinking of transistor dimensions can continue unhindered.

Dr. Murali highlighted chemical quantization — which allows changes in device parameters, as well as energy quantization — which leads to changes in the fundamental current-voltage characteristics of a transistor. A material’s resistance can also change in the nanoscale regime.

GIDL or gate-induced drain leakage is quite relevant to low power devices. GIDL leakage currents are becoming prohibitively high. While HKMG has solved the tunnelling problem, the GIDL issue still remains. Rotating the conventional wafer from <110> to <100> reduces the GIDL by an order of magnitude.

Next, what’s the alternative to CMOS devices? These could be 3D transistors with better gate control at 15nm and beyond as well as carbon nanotubes. I checked the Web: carbon nanotubes are molecular-scale tubes of graphitic carbon with outstanding properties. They are among the stiffest and strongest fibres known, and have remarkable electronic properties and many other unique characteristics. Excellent!

Finally, how do you pattern all of these devices? Computational lithography enables density scaling. Challenges include pattern optimization tool, code parallelization, HPC and optics.

Spin electronics could be the next evolution — leading to spintronics devices at nanoscale.  Here, IBM’s Giant Magnetoresistive Head, which has been a giant leap for IBM Research, comes into play.

Social product innovation

Manjunatha Hebbar, VP & Head - Strategic Services, HCL Technologies.

Manjunatha Hebbar, VP & Head - Strategic Services, HCL Technologies makes a point!

In his keynote, Manjunatha Hebbar of HCL Technologies stressed that innovation is required at every level across the entire value chain. A compelling alternative would be the social product innovation, or democratization of product innovation.

Benefits of social product innovation are manifold. The prime ones are —
* right product for the right market at the right time at the right price;
* lowest direct cost; sharing of risk and reward;
* real-time on demand access to resources; and
* organic transformation with the market.

He cited the example of Apple’s iPhone, which was launched during the peak of recession. The rest is history, as this smartphone went on to change the dymanics of the mobile phone market!

Hebbar highlighted that the society itself has core values of social product innovation. The core purpose — help everyone have their lives! The focus should be on process innovation and prodct innovation, leading to business innovation.

Today, everyone is on the cloud, mobile, connected and reading everyone. Creative commons is the most accepted license model today. Co-creation is always welcome.

Xilinx to build next-gen FPGAs on 28nm high-k metal gate

February 22, 2010 Comments off

Xilinx intros world’s first ultra-high-end FPGA based on 28nm high-k metal gate.

Xilinx intros world’s first ultra-high-end FPGA based on 28nm high-k metal gate.

Xilinx Inc. has announced the foundation for a next-generation of Xilinx programmable platforms that will give system designers FPGAs that consume half the power at twice the capacity than previously possible for addressing the Programmable Imperative.

Xilinx’s architecture for next-generation FPGA products will be built on 28nm high-k metal gate (HKMG), high-performance, low-power process at TSMC and Samsung.

According to Suresh  Menon, vice president, product development, Programmable Platforms Development, features of the next-generation FPGAs include:

* Reducing total power consumption enables customers to meet system integration and high-performance targets within their power budgets.
* Scalable unified architecture reduces customers’ investment developing and deploying products.
* Xilinx maximizes the value of 28nm with high-performance, low-power process to accelerate platforms for addressing the programmable imperative.

He highlighted some industry challenges. These include the decline ASICs — with development costs, risk and complexity, and time to market being 2x per node, leading to ASIC starts being 50 percent less per node and the ASIC business at -5 percent per year. The ASSP business model is also challenged. While it has grown at 22 percent CAGR from 2004-2009, the operating margins have declined by 27 percent, thus making tier 2 unsustainable.

Menon cited some examples addressing the programmable imperative — wireless communications, wired communications, industrial scientific and medical (ISM), automotive, consumer, and aerospace and defense.

Lower power initiatives are universal. The challenge is to lower the total power consumption, This has to be achieved without giving up on performance or differentiation. Some examples include: green base stations to reduce carbon footprint, eco-friendly server complexes and communication hubs, automotive power restricted environment, and size, weight, and power requirements in defense.

Consumer demand is also driving network bandwidth. A challenge would be enable 1Terabit switch fabric and 400+Gbps line cards. This could been addressed by providing support for 1+Tbps full-duplex bandwidth for high-end switch fabric, enabling high-performance, non-blocking capability with flexibility to integrate QoS security, etc., and extending support for 40G, 100G, 200G, and 400G line cards.

Menon said, “We are delivering lower power through technology innovation, enabling the lowest power, high performance FPGA.”  This is being done as follows:

* Reduce static power consumption by 50 percent.
– 28nm high-K metal gate high-performance, low power process reduces static power compared to 28nm high performance process.
* Lower dynamic power consumption using architectural innovations.
– Transistor choice and multi-gate oxide techniques reduce dynamic power consumption despite trends.
* Enable additional 20 percent power reduction using advanced tool innovations.
– Clock gating technology.
– Fifth generation partial reconfiguration. Read more…

Categories: 28nm, FPGA market, FPGAs, HKMG, Xilinx
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