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IEF 2013: New markets and opportunities in sub-20nm era!

October 15, 2013 1 comment

Future Horizons hosted the 22nd Annual International Electronics Forum, in association with IDA Ireland, on Oct. 2-4, 2013, at Dublin, Blanchardstown, Ireland. The forum was titled ‘New Markets and Opportunities in the Sub-20nm Era: Business as Usual OR It’s Different This Time.” Here are excerpts from some of the sessions. Those desirous of finding out much more should contact Malcolm Penn, CEO, Future Horizons.

Liam BritnellLiam Britnell, European manager and Research Scientist, Bluestone Global Tech (BGT) Materials spoke on Beyond Graphene: Heterostructures and Other Two-Dimensional Materials.

The global interest in graphene research has facilitated our understanding of this rather unique material. However, the transition from the laboratory to factory has hit some challenging obstacles. In this talk I will review the current state of graphene research, focusing on the techniques which allow large scale production.

I will then discuss various aspects of our research which is based on more complex structures beyond graphene. Firstly, hexagonal boron nitride can be used as a thin dielectric material where electrons can tunnel through. Secondly, graphene-boron nitride stacks can be used as tunnelling transistor devices with promising characteristics. The same devices show interesting physics, for example, negative differential conductivity can be found at higher biases. Finally, graphene stacked with thin semiconducting layers which show promising results in photodetection.

I will conclude by speculating the fields where graphene may realistically find applications and discuss the role of the National Graphene Institute in commercializing graphene.

Jean-Rene Lequepeys, VP Silicon Components, CEA-Leti, spoke on  Advanced Semiconductor Technologies Enabling High-Performance Jean-Rene Lequepeysand Energy Efficient Computing.

The key challenge for future high-end computing chips is energy efficiency in addition to traditional challenges such as yield/cost, static power, data transfer. In 2020, in order to maintain at an acceptable level the overall power consumption of all the computing systems, a gain in term of power efficiency of 1000 will be required.

To reach this objective, we need to work not only at process and technology level, but to propose disruptive multi-processor SoC architecture and to make some major evolutions on software and on the development of
applications. Some key semiconductor technologies will definitely play a key role such as: low power CMOS technologies, 3D stacking, silicon photonics and embedded non-volatile memory.

To reach this goal, the involvement of semiconductor industries will be necessary and a new ecosystem has to be put in place for establishing stronger partnerships between the semiconductor industry (IDM, foundry), IP provider, EDA provider, design house, systems and software industries.

Andile NgcabaAndile Ngcaba, CEO, Convergence Partners, spoke on Semiconductor’s Power and Africa – An African Perspective.

This presentation looks at the development of the semiconductor and electronics industries from an African perspective, both globally and in Africa. Understanding the challenges that are associated with the wide scale adoption of new electronics in the African continent.

Electronics have taken over the world, and it is unthinkable in today’s modern life to operate without utilising some form of electronics on a daily basis. Similarly, in Africa the development and adoption of electronics and utilisation of semiconductors have grown exponentially. This growth on the African continent was due to the rapid uptake of mobile communications. However, this has placed in stark relief the challenges facing increased adoption of electronics in Africa, namely power consumption.

This background is central to the thesis that the industry needs to look at addressing the twin challenges of low powered and low cost devices. In Africa there are limits to the ability to frequently and consistently charge or keep electronics connected to a reliable electricity grid. Therefore, the current advances in electronics has resulted in the power industry being the biggest beneficiary of the growth in the adoption of electronics.

What needs to be done is for the industry to support and foster research on this subject in Africa, working as a global community. The challenge is creating electronics that meet these cost and power challenges. Importantly, the solution needs to be driven by the semiconductor industry not the power industry. Focus is to be placed on operating in an off-grid environment and building sustainable solutions to the continued challenge of the absence of reliable and available power.

It is my contention that Africa, as it has done with the mobile communications industry and adoption of LED lighting, will leapfrog in terms of developing and adopting low powered and cost effective electronics.

Jo De Boeck, senior VP and CTO, IMEC, discussed Game-Changing Technology Roadmaps For Lifescience. Jo De Boeck

Personalized, preventive, predictive and participatory healthcare is on the horizon. Many nano-electronics research groups have entered the quest for more efficient health care in their mission statement. Electronic systems are proposed to assist in ambulatory monitoring of socalled ‘markers’ for wellness and health.

New life science tools deliver the prospect of personal diagnostics and therapy in e.g., the cardiac, neurological and oncology field. Early diagnose, detailed and fast screening technology and companioning devices to deliver the evidence of therapy effectiveness could indeed stir a – desperately needed – healthcare revolution. This talk addresses the exciting trends in ‘PPPP’ health care and relates them to an innovation roadmap in process technology, electronic circuits and system concepts.
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IMEC’s 450mm R&D initiative for nanoelectronics ecosystem

November 1, 2012 Comments off

Roger de Keersmaecker, IMEC, Belgium, presented on IMEC’s 450mm R&D initiative in support of the nanoelectronics ecosystem at the Semicon Europa event in Dresden, Germany. IMEC has prepared an integrated 450mm R&D initiative. This will present an innovation engine supporting the global nanoelectronics ecosystem.

IMEC will play a key role in the acceleration of 450mm equipment development by timely installation of alpha/beta-demo tools for early learning, in an industry-relevant technology flow and ensuring patterning capability by early 2016. The 450mm R&D pilot line will enable full 450mm process capability for advanced nodes by early 2017.

Source: IMEC, Belgium.

Source: IMEC, Belgium.

Scaling
Logic device scaling slows down and ‘interim’ nodes are likely to be introduced. Disruptive devices are needed beyond 10nm. NAND flash is migrating from 2D floating gate to 3D SONOS device architecture.

Emerging memories are being introduced at 1x nm node. The parallel system scaling path done using 3D TSV technology is established and slowly gaining in momentum. Die cost is also exploding. There is an increasing need for an innovation pipeline, early design/technology co-optimization and cost reduction.

IMEC announced the opening of 300mm CR expansion on June 8, 2010. The cleanroom expansion is 450mm ready. There is 1,200m2 extra clean room space, and ready for EUV. Fab 1 is a 200mm pilot line and 5200 m2 CR (1750 m2 Class 1), with 24/7 continuous operation. Fab 2 is a 300mm pilot line with ball room, clean sub-fab, and 3200 m2 + 1200 m2 CR, also in 24/7 continuous operation.

IMEC started engineering new 450mm clean room in 2012. It has plans to stat constructing the clean room in 2013 and complete by 2015. The Flemish Minister of Innovation, Ingrid Lieten, announced to invest in the building of imec’s 450mm clean room facilities.

With the combination of a state-of-the-art 300mm clean room and the transition to 450mm, imec will be able to keep on delivering its partners topnotch research on (sub)-10nm devices enabling the future growth of the global nanoelectronics industry.
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III-V high mobility semiconductors for advanced CMOS apps

October 30, 2012 Comments off

Clement Merckling, IMEC, Belgium, presented on the epitaxial growth and in-situ passivation requirements for III-V high mobility semiconductors for advanced CMOS applications at the Semicon Europa in Dresden, Germany.

The motivations for III-V MOS transistors include higher electron carrier mobility (@ low-field), more efficient source injection, smaller energy bandgap, VDD scaling, band engineering capabilities, lower temperature processing, high-K gate first process possible and 3D compatible architecture.

IMEC III-V EPI.

IMEC III-V EPI.

The International Technology Roadmap for Semiconductors (ITRS) believes in Ge and III-V. IMEC epi + in-situ oxide ‘tool park’ involves MBE (molecular beam epitaxy) and MOVPE (metalorganic vapour phase epitaxy) III-V growth techniques. The III-V EPI is clustered with in-situ oxide capabilities.

The AIXTRON Crius 300mm looks at III-V selective epitaxial growth (III-As and III-P). The AMAT/RIBER III-V logic cluster 300mm looks at the III-V selective epitaxial growth (III-As and III-P), in-situ surface analysis, handled by RIBER ISA 300, and oxide (ALD and MBE) chambers in-situ. The RIBER MBE 49 cluster 200mm looks at the III-V solid source epitaxy (III-As and III-Sb) oxide chamber in-situ.

Main issues and challenges
Main issues for III-V integration include III-V integration on Si platform. There are all sorts of crystalline defects. Next, gate stack formation on MOS. It is much more difficult to passivate interfaces. Smaller bandgap, means, an increased Ioff due to band-to-band-tunneling.

Challenges with III-V heteroepitaxy on Si include Lattice mismatch, anti-phase boundaries (APB), mismatch stress relaxation and related defects such as dislocations at interface, and extended defects (threading arms, SFs). There are other defects caused at isolation interfaces, such as twins, stacking faults, facets, etc. Finally, there is interdiffusion at heterogeneous interfaces.

However, it is possible to achieve high quality heteroepitaxy by direct epitaxy using metamorphic buffer and defect confinement and wafers bonding. Strain relaxed buffer (SRB) is among the options for III-V materials integration at imec.

There can be InGaAs metamorphic buffer, with the MBE growth of low defect density and device quality III-V heterostructure using a suitable metamorphic buffer. Or, there can be III-Sb on Si by SS-MBE, that provides a route to relax III-V.

Defect confinement is possible via ‘necking effect’. The selective area growth (SAG) of III-V compounds via MOVPE (or CBE ?) means the defects are trapped at trench edges. The other way is dislocation trapping in narrow STI trenches for aspect ratio >2. There is low defect density material in the upper part of the trench.

Elimination of APBs for on-axis Si (001), Si recess engineering, is possible either via rounded-Ge surface or V-grooved surface. In the rounded-Ge surface, step creation is done by surface engineering of a Ge seed layer. Double steps on a Ge surface are more stable and easy to form with a lower thermal budget than on Si.

In V-grooved surface, (111) surface is obtained either by KOH or TMAH wet etching. Growth inside a pre-defined Si {111} enclosure promote initial III-V nucleation uniformity.

The ‘necking effect’ approach presents its own challenges. One, perpendicular view, where there is efficient defect necking effect with side wall and parallel view, which allows viewing high defect density.
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IEF 2012: Turning recession into opportunity!

October 22, 2012 1 comment

Future Horizons recently organized and held the 21st Annual Electronics Forum on Oct. 3-5 at Bratislava, Slovakia. Here are excerpts from some of the proceedings:

Mojy Chian

Mojy Chian

Mojy Chian, senior VP Design Enablement. GlobalFoundries presented on ‘Foundry 2.0: The Era of Collaborative Device Manufacturing.’: Despite some predictions to the contrary, the foundry-based fabless model is not going away, and moreover it is driving manufacturers and device designers closer together. But like all living organisms, especially those in electronics, we have to continue to evolve. There are warning signs, both technical and economic, emerging in the foundry business that warrant our attention, and in fact require a re-thinking of how best to apply our resources and energy.

Recent talks of fabless companies investing in their own fabs, and of foundries developing ‘single company fabs’ underscore the sense of urgency. Clearly, we must change – Call it Foundry 2.0! This will be driven, ironically, by a move toward a more IDM-like model. Strategic collaboration that creates a ‘virtual IDM-like interface’ to chip design companies will help further close the gap between process teams at the manufacturing companies and design teams at the fabless companies.

With daunting technical challenges like 3D stacking, 450mm fabs, new transistor architectures, multipatterning, and the long-term viability of extreme ultraviolet (EUV) lithography, collaboration – early, often and deep – is really the only practical approach given the cost and complexities involved.

John Lofton Holt. founder, and chairman of the Board of directors. Achronix, presented on “Embedded FPGAs – Enabling The Next Generation Of Flexible SoCs.’: The system-on-chip (SoC) ecosystem is at a fundamental crossroads. With total

John Holt

John Holt

chip development and manufacturing costs exceeding $100 million at 22nm, it is no longer cost effective for most SoC designers to build a discrete chip for every application. As a result, SoC designers are investing in programmable intellectual property (IP) for IO expansion, emerging standards compliance and application acceleration.

This programmable IP ranges from microcontrollers and processors to simple state machines that are register-programmable. Nearly every SoC built today has some kind of programmable IP. The programmable logic industry is addressing this SoC challenge in a different way. Coming from the “other end of the spectrum”, the major public FPGA manufacturers are implementing more and more hard IP on their dies to reduce the area penalty of the programmable logic for specific applications.

These techniques, while effective for some mid-range volume applications, will not scale to high volume SoCs. The major public FPGA companies are also very hesitant to license their programmable fabric to SoC designers, fearing competition in their core markets and erosion of margins.

Rudy Lauwereins

Rudy Lauwereins

Rudy Lauwereins, VP Smart Systems Technology Office, IMEC, presented on ‘Providing “Insite” In The Unknown Design Space’: As technology scaling nears the “final frontier”, designers are confronted with an increasing number of restrictions.

Printing smaller and smaller features remains possible, but requires more and more regular layout patterns. Transistors can still be reduced in size, but may fall short of meeting electrical specifications. Smaller wires are becoming a performance bottleneck.

As technology scaling becomes less ideal, established design paradigms start to break. Creative and innovative solutions are required to sustain the momentum of Moore’s law: hitting the sweet-spot for cost and performance requires tight interaction between the technology development community and the design community. In an increasingly fabless world, imec’s Insite program builds the bridges between these communities.
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Need to work toward sustainable future: imec

September 5, 2011 2 comments

Luc Van den hove, president and CEO, imec.

Luc Van den hove, president and CEO, imec.

At an ISA CXO Conclave, Luc Van den hove, president and CEO, imec, said that we need to work toward a sustainable future. Started in 1984, Leuven, Belgium-based imec performs world leading research in nanoelectronics. He touched upon some research programs currently undertaken by imec.

Green radio is for low-power wireless communications. Technologies would be 1000K energy efficient. He added: “We are also developing low cost, low-power reconfigurable radios. Further, we feel that videos will dominate mobile phones.”

Another innovation, E-Nose, can be used for air quality, safety, food and well being. Human++ BAN life sciences, is yet another innovation. Now, the cost of healthcare is said to be exploding. By 2030, over 1 billion people will be over 65+ years. imec is developing body area network. According to imec, wearable wireless sensors can grow to over $400 million by 2014.

imec is working on technologies ranging from bio sensors to lab-on-chip. “We are also working on implantable devices such as microprobes,” said Van den hove. imec is also working on the NVision technology. According to estimates, there will likely be 78.1 million 3D TVs by 2012. Van den hove said, “we are developing holographic visualization.”

On energy, he said that renewable energy was growing in importance. “We are working on solar, storage, switching, etc. As an example, we have replaced Ag (silver) with Cu (copper) metallization.” Organic solar cells is yet another technology imec’s working on.”

In power electronics, imec is working on GaN power devices. “We also have a program for boosting chip performance and system functionality,” he added. “We are also exploring the third dimension — DRAM on logic.”

CMORE, is said to be more than CMOS, as well as MEMS, sensors, photonics, SiGe based metals/devices. In organic electronics, imec and Holst have developed the first plastic microprocessor, which was introduced in 2011. imec has research programs for full ecosystems as well.

Van den hove noted: “We also celebrate the launch of imec India. We want to develop sustainable nanoelectronic solutions. For example, rural India drives the mobile phone growth. India is also driving e-health.” In Arise Labs, imec has provided the nanoelectronic platform, technology and design expertise, application programming and strong industry network.

Arise Labs — an imec, Wipro initiative! Does it fit the bill?

September 5, 2011 1 comment

Belgium’s imec Corp. has collaborated with India’s Wipro Technologies to form the Arise Labs. Besides, imec has also opened its India office in Bangalore, according to Luc Van den hove, president and CEO, imec, at an India Semiconductor Association (ISA) CXO Conclave this evening.

On this same day, Cadence Design Systems (India), announced with imec Europractice IC Service, to develop a shuttle program for Cadence University Software Program members. Without a doubt, this news is of more importance, but Cadence, as well as imec, surprisingly, chose to underplay it, for now. Nevertheless!

Dr. Pradip Dutta, chairman, ISA.

Dr. Pradip Dutta, chairman, ISA.

On the Arise Labs event, Dr. Pradip Dutta, chairman, ISA raised an interesting query in his opening remarks: How do we bring the research quotient into the Indian semiconductor industry? He added that imec had most recently become an ISA member. imec has a huge focus on R&D as well.According to him, innovation to incubation to wealth creation was key!

Dr. Anurag Srivastava, CTO and senior VP, Wipro Global IT Business, said that emerging markets comprised 80 percent of the global population. Around 50 percent of the population in emerging markets was below 25 years of age. The rural population comprised 75 percent, and 64.7 percent users were those involved in high-tech adoption.

Overcoming challenges were essential to sustaining growth. In this regard, new service models and solutions

Dr. Anurag Srivastava, CTO and senior VP, Wipro.

Dr. Anurag Srivastava, CTO and senior VP, Wipro.

were required to overcome challenges. As an example, remote health monitoring could be used to address this challenge.

There is now an opportunity for new service models. These could be achieved in some of the following ways:
* Quality and reach of education through technology.
* Affordable healthcare through remote patient care and telemedicine.
* Address growing energy needs at affordable rates.

Dr. Srivastava laid out certain technologies that could be solutions for emerging markets. These are: intelligent machine to machine cyber convergence, natural user experience (NUE) technology, big data, web science and nano technologies. The ecosystem for  emerging market solutions include the following: medical, securities, automotive and aerospace, energy, and HPC/cloud.

He announced the Arise — Applied Research & Intelligent System Engineering, an R&D collaboration between imec and Wipro, that should try and take on all of the above mentioned challenges.

Coming back to the original headline of this post — does the imec and Wipro collaboration fit the bill? Perhaps, no! Here’s why!

The Cadence-imec collaboration is likely to allow Indian universities with unprecedented access to advanced technologies, enabling students to work with state-of-the-art process and design techniques through to silicon tape-out. Also, as part of the agreement, Cadence will offer support to its University Software Program members by providing flows and methodologies, while imec will provide access to IC technologies down to 65nm, SPICE models, design rules, PDKs, and standard cell libraries.

Wonder, what kept them from even mentioning it!

Categories: Arise Labs, Cadence, IMEC, Wipro
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