Archive for the ‘industrial segments’ Category

Altera on FPGAs outlook for 2009

December 28, 2008 Comments off

Hardly any segment of the global semiconductor industry has escaped the economic financial crisis! Nevertheless, as the year draws to a close, several segments are planning strategies for tackling what could well be a difficult 2009! FPGAs are no exception!

Jennifer Lo, Senior Marketing Manager, Altera Asia Pacific, agrees. Highlighting the impact, as per reports in the media, the economical environment we are getting into is extremely challenging. Recently, Gartner lowered its 2009 semiconductor forecast to ‘down 16 percent’ as compared to 2008.

Altera placed strongly
Lo says that compared to the other semiconductor companies, many of whom are taking very drastic measures in cutting down costs and preserving capital, Altera is in a very strong position, both financially and product-wise.

Financially, Altera is said to have taken steps to focus on cost reductions and simplification internally, a few years ago. The company is seeing great results from those efforts. “You may check our financial data and find that we are essentially debt-free and have very healthy balance sheet. We continue to be profitable even under the very challenging environment we are in,” Lo contends.

Product-wise, Altera announced a few days ago that it is shipping the industry’s 40nm product, considered a key milestone. “We are very excited about it with this new product family, Stratix IV, which offers the industry’s largest density, highest performance, highest system bandwidth and lowest power, targeting customers in a variety of markets, including communications, broadcast, test, medical and military,” she says.

Going forward in 2009, Altera will continue to rollout the rest of the members in the Stratix IV product family. It will also continue to execute new product strategies in the plan with full confidence.

Tackling demand weakness in FPGAs
There have been whispers regarding demand weakness in the FPGA industry. On the contrary, Lo adds that lower power, lower cost and smaller space are still common needs for portable applications for 2009. These needs may drive PLD vendors to focus on architecture and process to address power and cost. Also, work on package to develop a smaller device. Altera’s goal is to still focus on these common needs.

The Altera MAX II Z already offers the lowest dynamic power and comparable static power in industry already. The company may focus more on package size on 2009.

Although leading-edge FPGAs are scaling to 40nm and beyond, have the tools caught up with these new and complex processes? She says that lowering power consumption and improving customer productivity have been the focus of Altera’s product strategies for the past few years.

Lo adds: “Lowering power consumption means lowering costs for customers, not only in the BOM cost (reducing heatsink or cooling requirement), but also the ongoing operating cost (fans, air-conditioning costs,…etc). At this day and age of ever increasing fuel and electricity costs, this is gaining significance in customers’ selection consideration. Seeing such a need, reducing device power consumption has been a major element in the company’s product planning and execution.”

Altera’s Max II Z product in the low-cost CPLD line offers the lowest dynamic power and static power in the industry that is catered for the portable applications. On the high end of the spectrum, with Stratix IV GX, for example, with the advanced 40nm process node, Altera utilizes the ‘Strained Silicon’ technology, lower core voltage of 0.9V, triple gate oxide, as well as low-K inter-metal dielectric material low power transceiver designs.

“In terms of design, we put in extra effort in lowering the overall power consumption in the transceivers as well as optimized DDR memory interfaces,” she notes.

Coupled with programmable power technology, which allows customers to use high performance (hence, high power consumption) circuitry for design along the critical path, while either using low-power circuit on other parts of the design or turning the logic blocks completely off while not in use, all process and design innovations work together toward one common goal of lowering the overall power consumption in the customer design.

Lo says: “In customer productivity improvement, we’ve invested in the feature sets in our design software, Quartus II, to enable team-based designs, incremental compilation, as well as faster compilation time compared to the other competing software. We also have a wide suite of IPs in a multitude of applications and technologies, such as our Nios embedded processors, the many memory interfaces and peripherals. Combining all of those with our SOPCBuilder tool also enables customers to integrate system designs with very much reduced time and effort.”

There have also been some talks lately about FPGA design starts being quite flat over the last couple of years.

Altera sees a lot of new market applications for FPGAs, apart from the traditional communications market. Out of the many market segments that it participates in, the company feels that communications, military and industrial segments will be in better situation than others in the next couple of years. Needless to say, Altera will continue to focus on these segments.

Tackling complexity
Tackling complexity is a major focus area for projecting FPGAs as a growth segment for 2009.

Lo says: that as with other previous downturns, the industry may go through its reformation, which may inevitably involve some weaker companies to either go out of business due to deteriorating business environment or get acquired by stronger companies. Altera is very confident that programmable logic, with its highly flexibility, versatile application, will have a good market position in 2009.

The Hardcopy ASIC is said to have been Altera’s major differentiator from the other PLD/FPGA vendors.

“We are the only company having both an FPGA vehicle to enable fast time-to-market and simultaneously possessing the seamless migration platform to low-cost production support using Hardcopy ASIC. With the industry trend of fewer and fewer ASIC starts due to the high NRE costs and high justifying volume, there will also be less investment in the ASSP front given the contracting demand. We see Hardcopy as a major competitive edge that will us bring to a different rank in the industry,” she notes.

Indeed, it is good to see companies thinking very hard about tackling a difficult 2009! There’s lot of fight left, and it’s not that semiconductor companies haven’t faced downturns earlier. Keep the faith and allow these folks to come up tops again!

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