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Integrating next-gen technology into nano/MEMS facilities

September 23, 2012 Comments off

CH2M HLL on nanomanufacturing.

CH2M HLL on nanomanufacturing.

CH2M HLL is a global leader in consulting, design, design-build, operations, and program management. Its ultimate goal is to link nanotechnologies to high-tech manufacturing.

Nanomanufacturing techniques for scale include photo-lithography techniques, e-beam lithography techniques, ion-beam lithography techniques, nano-imprint lithography, nanofabrication by self-assembly and laser technology processes.

There are three major challenges for cost-effective nanomanufacturing — flexibility, critical environment scale-up and safety, sustainability and health (SSH). Also, nanomanufacturing requires high flexibility. Nanofacility critical environments include electromagnetic interference, cleanliness, vibration, temperature and humidity control, adaptive HVAC zones, airborne molecular contamination (AMC) and acoustics.

There are nano facility site planning challenges such as surface transit, direct current light rail, high voltage lines and truck and bus traffic. There is a need to analyse the detailed ambient conditions study and subsurface vibration testing, which is 3-4 meters below grade. Solutions include ‘no-build zones for vibration, EMI and RFI, building outside zones, identify ‘sweet spot’, VC-E lower/first level, and remediation by mass such as slab size lower level and slab size first level.

The proposed model for CH2M HLL’s China nanomanufacturing includes top level R&D labs, stacked cleanrooms for pilot and manufacturing, nano/MEMS/NEMS, ISO 5 and 7 cleanrooms, VC-D and VC-C vibration criteria, E-beam metrology, TEM suite capability and remote bulk gas pad. The proposed China baseline is in Suzhou, China.

Headquartered in Englewood, Colorado, USA, CH2M HLL has nearly 30,000 employees. Broadly diversified across multiple business sectors, it had $6.4 billion in revenue (2011).

EDA Tech Forum 2010: Nanoscale regime and social product innovation!

August 18, 2010 Comments off

This a continuation of my coverage of the Mentor Graphics’ EDA Tech Forum 2010.

Here, I shall discuss the main points of the two keynotes by Dr. Kota Murali, lead scientist & program manager of nanotech, IBM India, and Manjunatha Hebbar, VP & Head – Strategic Services, HCL Technologies Ltd — my good friend and fellow board member at the Indian Microelectronics Academy (IMA).

Nanotech for a smarter planet

Dr. Kota Murali, lead scientist & program manager of nanotech, IBM India.

Dr. Kota Murali, lead scientist & program manager of nanotech, IBM India @ EDA Tech Forum 2010.

Dr. Kota Murali, lead scientist & program manager of nanotech, IBM India, presented on nanotech for a smarter planet. The motivation for nanotech at IBM has been — since IT has grown as devices have shrunk. Now, we have reached the nanoscale level. The challenge is: how do we take new technologies to markets?

He briefly touched upon IBM’s latest generation processor, the Power7, built on 45nm. The next generation Power8 processors are supposed to be built on 22nm/32nm.

He said that physical and chemical properties of materials depend on the size. Hence, it is important to use nano and quantum scale properties for next generation devices. There is this classical scaling reality — to maintain generational performance gains, supply voltage is not scaled ideally, leading to major power issues.

In the future, innovation, scaling and power will drive performance. Power will play a critical role in developing next-generation products.

On the novel high-K metal gate (HKMG) devices, these gates are already four monolayers thick. We need HKMG since it significantly reduces gate leakage and chips consume lesser power. Also, it allows equivalent oxide thickness. The shrinking of transistor dimensions can continue unhindered.

Dr. Murali highlighted chemical quantization — which allows changes in device parameters, as well as energy quantization — which leads to changes in the fundamental current-voltage characteristics of a transistor. A material’s resistance can also change in the nanoscale regime.

GIDL or gate-induced drain leakage is quite relevant to low power devices. GIDL leakage currents are becoming prohibitively high. While HKMG has solved the tunnelling problem, the GIDL issue still remains. Rotating the conventional wafer from <110> to <100> reduces the GIDL by an order of magnitude.

Next, what’s the alternative to CMOS devices? These could be 3D transistors with better gate control at 15nm and beyond as well as carbon nanotubes. I checked the Web: carbon nanotubes are molecular-scale tubes of graphitic carbon with outstanding properties. They are among the stiffest and strongest fibres known, and have remarkable electronic properties and many other unique characteristics. Excellent!

Finally, how do you pattern all of these devices? Computational lithography enables density scaling. Challenges include pattern optimization tool, code parallelization, HPC and optics.

Spin electronics could be the next evolution — leading to spintronics devices at nanoscale.  Here, IBM’s Giant Magnetoresistive Head, which has been a giant leap for IBM Research, comes into play.

Social product innovation

Manjunatha Hebbar, VP & Head - Strategic Services, HCL Technologies.

Manjunatha Hebbar, VP & Head - Strategic Services, HCL Technologies makes a point!

In his keynote, Manjunatha Hebbar of HCL Technologies stressed that innovation is required at every level across the entire value chain. A compelling alternative would be the social product innovation, or democratization of product innovation.

Benefits of social product innovation are manifold. The prime ones are —
* right product for the right market at the right time at the right price;
* lowest direct cost; sharing of risk and reward;
* real-time on demand access to resources; and
* organic transformation with the market.

He cited the example of Apple’s iPhone, which was launched during the peak of recession. The rest is history, as this smartphone went on to change the dymanics of the mobile phone market!

Hebbar highlighted that the society itself has core values of social product innovation. The core purpose — help everyone have their lives! The focus should be on process innovation and prodct innovation, leading to business innovation.

Today, everyone is on the cloud, mobile, connected and reading everyone. Creative commons is the most accepted license model today. Co-creation is always welcome.

Measuring performance of carbon nanotubes as building blocks for ultra-tiny computer chips of the future

October 15, 2007 Comments off

There is this really great story from IBM Research Labs that I simply have to seed here for my readers.

IBM’s scientists have created a method to measure the performance of carbon nanotubes as building blocks for ultra-tiny computer chips of the future. Of course, you can also read it on IBM Research Lab’s site as well as on CIOL’s semicon site.

IBM scientists have measured the distribution of electrical charges in tubes of carbon that measure less than 2nm in diameter, 50,000 times thinner than a strand of human hair.

This novel technique, which relies on the interactions between electrons and phonons, provides a detailed understanding of the electrical behavior of carbon nanotubes, a material that shows promise as a building block for much smaller, faster and lower power computer chips compared to today’s conventional silicon transistors.

Phonons are the atomic vibrations that occur inside material, and can determine the material’s thermal and electrical conductivity. Electrons carry and produce the current. Both are important features of materials that can be used to carry electrical signals and perform computations.

The interaction between electrons and phonons can release heat and impede electrical flow inside computer chips. By understanding the interaction of electrons and phonons in carbon nanotubes, the researchers have developed a better way to measure their suitability as wires and semiconductors inside of future computer chips.

In order to make carbon nanotubes useful in building logic circuitry, scientists are pushing to demonstrate their high speed, high packing density and low power consumption capabilities as well as the ability to make them viable for potential mass production.

Dr. Phaedon Avouris, IBM Fellow and lead researcher for IBM’s carbon nanotube efforts, said: “The success of nanoelectronics will largely depend on the ability to prepare well characterized and reproducible nano-structures, such as carbon nanotubes. Using this technique, we are now able to see and understand the local electronic behavior of individual carbon nanotubes.”

To date, researchers have been able to build carbon nanotube transistors with superior performance, but have been challenged with reproducibility issues. Carbon nanotubes are sensitive to environmental influences.

For example, their properties can be altered by foreign substances, affecting the flow of electrical current and changing device performance. These interactions are typically local and change the density of electrons in the various devices of an integrated circuit, and even along a single nanotube.

France rising in nanotech excellence

October 9, 2007 Comments off

This was sent to me by the French Technology Press Office in New Delhi. Reproduced here for readers.

More and more companies from the USA and Japan are investing and launching partnerships in France to take advantage of its cutting-edge nanotechnology expertise. France boasts several zones dedicated to advancing nanotechnology excellence, including the SCS cluster in Sophia Antipolis, the Systematic cluster in the Paris region and notably, the global micro-nanotechnology cluster Minalogic in Grenoble.

In 2007, Minalogic will strengthen its leader status by investing €80 million into 8 new collaborative projects focused on micro and nanotechnologies for next-generation semiconductors and new manufacturing processes, and it recently welcomed Hewlett-Packard as its 50th partner. Starting in September, HP will help cluster members save valuable amounts of time and money with access to highly advanced 2-TeraFlop data processors, called Virtual Nodes.

On the research side, France’s world-class nanotech laboratory CEA-Leti and the leading Japanese lithography company Nikon announced a joint effort to examine Double Patterning and Double Exposure technology for 32 nm semiconductor devices. “Leti offers an outstanding, state-of-the-art facility with all of the processes required for Double Patterning,” says Toshikazu Umatate, Executive Officer, Precision Equipment Co., Nikon Corp. Another Japanese leader, Yamatake, is already working with Leti to develop nanotechnologies.

International companies looking to expand in nanotechnology are also choosing France for their European headquarters. The California-based analog semiconductor company Monolithic Power Systems, ranked as one of the fastest growing companies in Silicon Valley by Deloitte, has now opened its headquarters in Bernin-Crolles, and Boc Edwards, part of the Linde Group, has also moved its European semiconductor business headquarters from London to Grenoble to be closer to its electronics customers and to recruit skilled talent in the region.

France’s expertise is expected to grow on the healthcare side of nanotechnologies following the recent announcement of the opening of Clinatec, an experimental nanotechnology-based neurosurgery clinic expected to be set up in the next three years. The clinic will benefit from the work being carried out at Minatec, Europe’s largest research center in micro-nanotechnologies.

Indian government announces policy to woo investments in semicon fabs

September 16, 2007 2 comments

Better late than never, as the saying goes. The Department of Information Technology, Ministry of Communication and IT, Government of India, needs to be congratulated for coming up with the Special Incentive Package Scheme (SIPS)to encourage investments for setting up semicon fabs, and other micro and nanotechnology manufacturing industries in India!

The “ecosystem units” have been clearly defined as units, other than a fab unit, for manufacture of semiconductors, displays including LCDs, OLEDs, PDPs, any other emerging displays; storage devices; solar cells; photovoltaics; other advanced micro and nanotechnology products; and assembly and test of all the above products.

Just a week or two back, I was in conversation with some companies from Israel who were looking to develop business in India. Now, they, and others, have clear guidelines to follow. One of the companies, Nova Measuring Instruments Ltd, should feel happy that the definition of “ecosystem” includes assembly and test of products.

Nova develops, produces, and markets advanced monitoring, measurement and process control systems for the semiconductor manufacturing industry. Another well-known player, Tessolve, has been present in India since 2005 and would surely feel glad with the notification. At least, the media and others will take more notice of the company.

In Hong Kong, an ex-colleague and I used to cover OLEDs. When I first read about this technology back in the early 2000, I used to wonder whether India could have such a capability. Seems, it is now in a position to have OLEDs! I hope Lite Array (OLED) HK is watching and reading all of this.

Plasma display panels is another interesting line. The guidelines should interest LG, Matsushita, Sichuan Changhong Electric Co. Ltd, IRICO Group Corp. Panasonic, Asahi, Mitsui Chemicals, Nippon Electric, Samsung etc. Some of these firms are already present in India in one form or the other. It’s just a matter of their being keen on developing PDP in India.

LCDs could be another big investment area. Taiwan’s AU Optronics (AUO), Chi Mei Optoelectronics (CMO), Sharp, Samsung, as well as other biggies like LG, NEC, etc., need to be wooed.

It really excites me to see all the possibilities in front of India. If this goes on well, India would be in for a great ride in electronics manufacturing, and in the semicon space.

In the same context, the Bangalore Nano 2007, which will be held in December, could not be better timed. There should be a whole lot of companies looking to be present at this show!

India’s now on the threshold of major initiatives in the electronics manufacturing space. Some semicon fabs will also come up, and the number of fabless companies should likely increase. Maybe, TSMC and Tower could oblige with some foundries too. Should all of this happen at the right time, we are in for exciting times.

Bangalore Nano puts Indian firmly on world nanotechnology map

August 23, 2007 Comments off

India is now firmly on the global nanotechnology map, following the announcement of the first Bangalore Nano 2007 Convention, which will be held this December.

The nanotechnology industry is heralding a new world order. It has been estimated that the market will grow to over US $1 trillion by 2015. In the US, nanotechnology projects have attracted more than US$800 million in public funds making it the largest research project since the Apollo moon landing.

The European Union is also committed to ensuring a balanced approach in developing nanotechnology. Japan has been investing in nanoscience since the 1980s and is now behind only to the USA in terms of government investment. South Korea and China have revised and improved their national initiatives over the past year, and Australia and India have announced significant new national investments in nanoscience and nanotechnology.

The first ever such Convention, a two-day event on nanoscience and technology, will be held on December 6-7, in association with Jawaharlal Nehru Centre for Advanced Scientific Research (JNCASR). It would focus on the integrated roles of technologies, applications and market for the successful commercialization of nanotechnology. The theme of the event is: ‘Bridging the research-industry gap in Nanotechnology’.

My colleague, Radhika, has actually written about Bangalore Nano 2007, and I’m merely borrowing that page link from CIOL Semicon home page.

Bangalore Nano 2007 is the first major event of its kind in the country and is likely to host renowned global scientists and industry veterans in the field of nanotechnology.

C.N.R. Rao, honorary president, Jawaharlal Nehru Centre for Advanced Scientific Research (JNCASR) and the Chief Mentor of Bangalore Nano 2007, said: “Nanotechnology, which has a global business potential of nearly $1 trillion, has many valuable societal application for the unprivileged in the country, including the creation of a more efficient filtering systems for producing clean drinking water and the provision of cheap and clean energy.”

This will surely be an event worth the wait

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