Archive for the ‘Neeraj Varma’ Category

Xilinx announces 20nm All Programmable UltraSCALE portfolio

December 11, 2013 Comments off

Xilinx Inc. has announced of its 20nm All Programmable UltraScale portfolio with product documentation and Vivado Design Suite support.

Neeraj Varma, director-Sales, India, Xilinx, said: “We are enabling All Programmable and smarter systems. We are using smart IP. We are aligning to produce smarter systems. We are helping customers to differentiate their products faster.

“In future, we will go with concurrent nodes with FPGAs, SoCs and 3D ICs. As per our estimates, 28nm will have a very long life. We shipped the 20nm device in early Nov. 2013. It complements 28nm or new high-performance architectures. 16nm complements 20nm with FinFET, multiprocessing, memory.”

Virtex UltraScale device.

Virtex UltraScale device.

Strategy execution has kept Xilinx a generation ahead. As of Dec. 2013, its 20nm portfolio is available to customers. There are two major announcements from Xilinx.

* Xilinx 20nm All Programmable UltraScale portfolio now available with ASIC-class architecture and ASIC-strength design solution.

* Xiilinx doubles industry’s highest capacity device to 4.4 mn logic, delivering density adantage, a full generation ahead.

KINTEX UltraSCALE – XCKU035, 040, 060, 075, 100, 115.
VIRTEX UltraSCALE – XCVU065, 080, 095, 125, 145, 160.

There is a family migration path. There is scalability for derivative applications. You can leverage PCB investment across platforms. It is future-proof with migration path to 16nm. For making these happen, Xilinx is using the TSMC 20SoC.

Varma added, “We have increased the logic cells in Kintex and Virtex, and added 100G Ethenet blocks and 150G Interlaken blocks.”

The second announcement – highest density in FPGAs in industry. The XCVU440 is the largest in the industry by 4X, a full generation ahead, and uses 50M equivalent ASIC gates. Xilinx is delivering an ASIC-class advantage through silicon, tools and methodology.

There is UltraSCALE ASIC-class architecture, and ASIC-class capabilities. There is also the Vivado ASIC-strength design suite.
UltraFAST is the design methodology. UltraSCALE will support networking, digital video and wireless.

Interconnect bottlenecks impede next generation performance.
* Routing delay dominates overall delay.
* Clock skew consumes more timing margin.
* Sub-optimal CLB packing reduces performance and utilization.

Varma added: “We have solved these issues – as UltraSCALE re-architects the core. There is 90 percent utilization now with maximum performance. We added next-generation routing, ASIC-like clocking – have clocks by segment, and logic cell packing.

“Block-level innovations optimize critical paths for massive bandwidth and processing. We are going to support DDR4, and there will be a lot more security features.”

The Vivado design suite accelerates productivity. Analytical placer solves the interconnect issue.

UltraSCALE apps include:
VIRTEX: 400G OTN switching, 400G transponder, 400G MAC-to-Interlaken bridge, 2x100G Muxponder, ASIC prototyping.
KINTEX: 4×4 mixed mode radio, 100G traffic manager NIC, super high-vision processing, 256-channel ultrasound, 48-channel T/R radar processing.

Xilinx Base Targeted Design Platform helps save months of development!

July 6, 2009 Comments off

Last week, Xilinx discussed its Targeted Design Platforms, aimed at accelerating the development of system-on-chip (SoC) solutions with Xilinx Virtex-6 and Spartan-6 FPGAs.

I was in conversation with Brent Przybus, Director of Product Marketing, as well as Neeraj Varma, Country Manager, Sales, for India and Australia and New Zealand.

First up, the ISE Design Suite 11.2 is now available for download, with full public support for Virtex-6 and Spartan-6 FPGA families. Xilinx also introduced the Spartan-6 and Virtex-6 base evaluation kits, which can be order immediately by customers.

Since this is the ISE Design Suite 11.2, Przybus added that prior to June 24, support for the Virtex-6 and Spartan-6 FPGA families was available only to early access customers.

Accelerating development of SoC solutions
Next, the Base Targeted Design Platform is said to accelerate the development of SoC solutions. According to Przybus, the Base Targeted Design Platform provides a framework that customers can extend to build their SoC solutions.

“We are providing the common functions including host interface and external memory controller as well as multi-boot in a system configuration. Customers can leverage this code saving weeks of months of development.”

Why now?
The obvious question, why this release now, and not earlier? According to Varma: “Xilinx has always had boards, silicon, tools, IP and reference designs. However, with changes in market conditions and customer needs evolving, what became abundantly clear in recent years is that we need a more formalized and efficient way of providing a base for customers to build upon. Customers have also been asking for more complete design solutions.”

The concept for Base Targeted Design Platform was introduced in February when Xilinx had announced the architectural details of Spartan-6 and Virtex-6 FPGA devices along with the entire targeted design platform strategy.

“When the announcement was made, we had early access customers designing with Spartan-6 and Virtex-6 FPGAs. With the release of the ISE Design Suite 11.2, we are opening up public access to the two new device families. By doing so, we are opening up access through software of all our new devices, we are also making technical documentation, user guides and other resources available to all customers,” he added.

The release of the Base Targeted Design Platform is coincidental to the public availability of software supporting both Virtex-6 and Spartan-6 FPGAs.

The new Virtex-6 FPGA and Spartan-6 FPGA Evaluation Kits are the first in a series of kits that Xilinx will offer throughout the year designed to simplify the evaluation and development of SoCs with the latest generation of programmable technologies from Xilinx.

Now that the first kits have been released, let us probe into Xilinx’s plan for evaluation kits that it will offer throughout the year.

Varma added: “According to our Targeted Design Platform strategy, we have introduced the first level of our offerings. Moving forward, throughout the year we will introduce the Domain Specific Platform and then the Market Specific Platform. The Domain Kits will incorporate embedded kits, connectivity kits, and finally the DSP kits for both Virtex-6 and Spartan-6.” This point should be noted with great care by designers as lots more is in the offing from Xilinx.

The Market Specific Platform will address specific markets and include Communication, Video and Broadcast Kits, Market specific IP, custom tools and custom boards, added Varma.

Spartan-6 SP601 evaluation kit
Xilinx also introduced the Spartan-6 SP601 evaluation kit. Brent Przybus highlighted that the Spartan-6 SP601 evaluation kit is designed to address customers developing high volume, lower cost applications.

He elaborated: “The kit features the Spartan-6 LX16 FPGA and ships with a full base reference design and interface software providing customers a host communications link, built-in memory controller core that interfaces to DDR2 DRAM on the SP601 board, support for multi-boot, and a processing block that enables customers to see and measure the benefits of using a hard IP vs. Logic only simple processing function.

Addressing defense, aerospace apps
How useful will be all of this for defense and aerospace applications? According to Neeraj Varma, a lot of aerospace and defense applications require high performance digital signal processing (DSP), for example, in their video processing, secure communications, wireless communications (software defined radio or SDR), etc.

“Using the Base Targeted Design PLtatform as shown in the demonstration video, designers will be able to evaluate tradeoffs in performance, precision, and power consumption using hard DSP slices available in Spartan-6 and Virtex-6 FPGAs,” he said.

Using the DSP slices in Spartan-6 will help designers boost their performance by five times with higher precision without resulting into the increase of overall power consumption.

Varma added: “The Base Targeted Platform that we have announced will help our customers tune their applications not only in the aerospace and defence applications, but can be used for other applications in different vertical markets as well. Through this year, we will introduce Domain Specific Kits followed by Market Specific Kits. The Market Specific Platform will further address the specific defense applications in future.”

Lastly, there has been a lot of focus on design re-engineering and design security.

Przybus pointed out that the specific reference design shown in the Xilinx demo video has been done in HDL and doesn’t include and design security.

“The base reference design is portable and can be extended in a number of ways. The customer could use the built-in features like DeviceDNA, AES encryption of bitstream, etc. in our Virtex-6 and Spartan-6 silicon to secure their designs,” he noted.

Programmable imperative: Changing semicon landscape!

February 14, 2009 Comments off

This post is based on a presentation recently made by Amit Dhir, Senior Director, Business Operations, Xilinx, prior to the launch of the Xilinx Virtex-6 and Spartan-6 FPGA families. Xilinx was very kind to share this with me, and I need to thank him and Neeraj Varma, Country Manager – Sales (India/ANZ) for Xilinx.

Xilinx’s next-generation FPGA families are said to enable new, targeted design platforms. Incidentally, Altera, too, decided to launch its Stratix IV GT and Arria II GX FPGAs, the same day as Xilinx.

Back to Dhir’s discussion on the programmable imperative and a changing semiconductor landscape! According to him, the key market trends changing the technology landscape include the empowered consumer, hyper-connectivity and social networking. In this scenario, time-to-market and flexibility are the key attributes for success.

Customer challenges today revolve around doing more with less, and now! Companies now need to monitor their market and competitive leadership, time-to-market and profitable growth, spiraling development cost, and risk aversion and product complexity. Business constraints are now forcing customers to reduce internal R&D investments. The graph shows the IC cost by process nodes.
Time for programmables NOW!
The time for programmables is now! It is an ideal technology to help combat customer challenges. The programmable imperative is driven by factors such as market forces, financial constraints and technology drivers. Really, it all boils down to accelerating the programmable imperative!

Looking back at the logic IC landscape, business dislocation has been underway for the incumbents. From 1998 through 2004, a significant amount of IP migrated from system OEMs to ASSP vendors, particularly in the communications market.

Even ASICs present a bleak outlook and are likely going the way of gate arrays! The graph here shows the declining ASIC market share.
The increasing development costs and reduced R&D investments by OEMs has been leading to accelerated erosion of ASIC market share going forward. In fact, the long-awaited tipping point where FPGAs replace gate arrays is upon us.

ASSP vendor challenges
Looking at ASSP vendors, those vendor in tier 1 face challenges such as business model viability and poor profitability. High risk environment leads to poor customer loyalty. The large capital outlay on fabbed is moving on to fablite and fabless. Next, market and customer consolidation means fewer deals for such vendors. Chase of >1M units means few applications and customers.

What about the tier 2 ASSP vendors challenge? They have been forced into very high volumes and compete poorly against the tier 1 vendors. Hence, profitability and business models are under severe pressure. It is to be noted that out of the 115-odd companies followed by the GSA (Global Semiconductor Alliance), 29 have market caps less than their cash.

As for the tier 3 ASSPs and startups challenge, the Round-A VC funding has dried up! Incidentally, the round-A funding (dollar amount) declined 82 percent from 2000 and 2007. Through Q308, only two chip companies received round-A funding, totaling $12 million.

Programmables next business disruption
Looking at the logic IC landscape, programmables are emerging as the next business disruption. FPGAs are no longer seen as a yearly cost burden prior to ASIC release, but more as a solution that could live in products and platforms over time.

The tipping point should happen in 2009, and programmables should reach a plateau of productivity by 2016!

Where Xilinx fits in!
Today, Xilinx sees growth opportunity ahead, and it is more of a pragmatic reality now! The company understands that new attributes are required to meet the challenges of the future. It lists three attributes to bring about this change:

* Transformation: Market led, semiconductor leader.
* Ushering in the era of targeted design platforms.
* World class, thriving third-party ecosystem.

Transformation is already underway at Xilinx, which is now becoming a market led, semiconductor business leader.

It is ushering in the era of targeted design platforms, which is enabling innovation. A view at the ASIC/ASSP class applications reveals that the positioning has become more market focused. The architecture is more toward market tuned platforms. Xilinx also focuses on low power leadership. Its design methodology has now become open, scalable and hierarchical.

Targeted design platforms also enable customers to do more, and faster, and focus on their differentiation! Xilinx also boasts a world class and thriving third-party ecosystem. The software and IP is scalable, standardized, extensible and collaborative.

Xilinx is striving to accelerate the programmable experience by giving what customers need, and when they need it! Its Virtex and Spartan silicon form the programmable foundation. It offers base targeted design platforms — devices, software, IP, boards, etc. It also offers domain specific platforms, along with domain specific IP and tools, as well as market specific platforms, which are inclusive of market specific reference designs and IP.

According to Dhir, the company is offering innovative technology to address diverse market requirements and to drive programmable logic beyond the tipping point!

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