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ST intros STM32F4 series high-performance Cortex-M4 MCUs

September 18, 2013 Comments off

STMicroelectronics has introduced the STM32F4 series STM32 F4x9 and STM32F401, which are high-performance Cortex-M4 microcontrollers (MCUs).

On the growth drivers for GP MCUs, the market growth is driven by faster migration to 32 bit platform. ST has been the first to bring the ARM Cortex based solution, and now targets leadership position on 32bit MCUs. An overview of the STM32 portfolio indicates high-performance MCUs with DSP and FPU up to 608 CoreMark and up to180 MHz/225 DMIPS.

Features of the STM32F4 product lines, specifically, the STM32F429/439, include 180 MHz, 1 to 2-MB Flash and 256-KB SRAM. The low end STM32F401 has features such as 84 MHz, 128-KB to 256-KB Flash and 64-KB SRAM.

The STM32F401 provides thebest balance in performance, power consumption, integration and cost. The STM32F429/439 is providing more resources, more performance and more features. There is close pin-to-pin and software compatibility within the STM32F4
series and STM32 platform.

The STM32 F429-F439 high-performance MCUs with DSP and FPU are:
• World’s highest performance Cortex-M MCU executing from Embedded Flash, Cortex-M4 core with FPU up to 180 MHz/225 DMIPS.
• High integration thanks to ST 90nm process (same platform as F2 serie): up to 2MB Flash/256kB SRAM.
• Advanced connectivity USB OTG, Ethernet, CAN, SDRAM interface, LCD TFT controller.
• Power efficiency, thanks to ST90nm process and voltage scaling.

In terms of providing more performance, the STM32F4 provides up to 180 MHz/225 DMIPS with ART Accelerator, up to 608 CoreMark result, and ARM Cortex-M4 with floating-point unit (FPU).

The STM32F427/429 highlights include:
• 180 MHz/225 DMIPS.
• Dual bank Flash (in both 1-MB and 2-MB), 256kB SRAM.
• SDRAM Interface (up to 32-bit).
• LCD-TFT controller supporting up to SVGA (800×600).
• Better graphic with ST Chrom-ART Accelerator:
— x2 more performance vs. CPU alone
— Offloads the CPU for graphical data generation
* Raw data copy
* Pixel format conversion
* Image blending (image mixing with some transparency).
• 100 μA typ. in Stop mode.

Some real-life examples of the STM32F4 include the smart watch, where it is the main application controller or sensor hub, the smartphone, tablets and monitors, where it is the sensor hub for MEMS and optical touch, and the industrial/home automation panel, where it is the main application controller. These can also be used in Wi-Fi modules for the Internet of Things (IoT), such as appliances, door cameras, home thermostats, etc.

These offer outstanding dynamic power consumption thanks to ST 90nm process, as well as low leakage current made possible by advanced design technics and architecture (voltage scaling). ST is making a large offering of evaluation boards and Discovery kits. The STM32F4 is also offering new firmware libraries. SEGGER and ST signed an agreement around the emWin graphical stack. The solution is called STemWin.

Moore’s Law could come to an end within next decade: POET

August 28, 2013 1 comment

Dr. Geoff Taylor

Dr. Geoff Taylor

POET Technologies Inc., based in Storrs Mansfield, Connecticut, USA, and formerly, OPEL Technologies Inc., is the developer of an integrated circuit platform that will power the next wave of innovation in integrated circuits, by combining electronics and optics onto a single chip for massive improvements in size, power, speed and cost.

POET’s current IP portfolio includes more than 34 patents and seven pending. POET’s core principles have been in development by director and chief scientist, Dr. Geoff Taylor, and his team at the University of Connecticut for the past 18 years, and are now nearing readiness for commercialization opportunities. It recently managed to successfully integrate optics and electronics onto one monolithic chip.

Elaborating, Dr. Geoff Taylor, said: “POET stands for Planar Opto Electronic Technology. The POET platform is a patented semiconductor fabrication process, which provides integrated circuit devices containing both electronic and optical elements on a single chip. This has significant advantages over today’s solutions in terms of density, reliability and power, at a lower cost.

“POET removes the need for retooling, while providing lower costs, power savings and increased reliability. For example, an optoelectronic device using POET technology can achieve estimated cost savings back to the manufacturer of 80 percent compared to the hybrid silicon devices that are widely used today.

“The POET platform is a flexible one that can be applied to virtually any market, including memory, digital/mobile, sensor/laser and electro-optical, among many others. The platform uses two compounds – gallium and arsenide – that will allow semiconductor manufacturers to make microchips that are faster and more energy efficient than current silicon devices, and less expensive to produce.

“The core POET research and development team has spent more than 20 years on components of the platform, including 32 patents (and six patents pending).”

Moore’s Law to end next decade?
Is silicon dead and how much more there is to Moore’s Law?

According to Dr. Taylor, POET Technologies’ view is that Moore’s Law could come to an end within the next decade, particularly as semiconductor companies have recently highlighted difficulties in transitioning to the next generation of chipsets, or can only see two to three generations ahead.

Transistor density and its impact on product cost has been the traditional guideline for advancing computer technology because density has been accomplished by device shrinkage translating to performance improvement. Moore’s Law begins to fail when performance improvement translates less and less to device shrinkage – and this is occurring now at an increasing rate.

He added: “For POET Technologies, however, the question to answer is not when Moore’s Law will end – but what next. Rather than focus on how many more years we can expect Moore’s Law to last – or pinpoint a specific stumbling block to achieving the next generation of chipsets, POET looks at the opportunities for new developments and solutions to continue advancements in computing.

“So, for POET Technologies, we’re focusing less on existing integrated circuit materials and processes and more towards a different track with significant future runway. Our platform is a patented semiconductor fabrication process, which concentrates on delivering increases in performance at lower cost – and meets ongoing consumer appetites for faster, smaller and more power efficient computing.”
Read more…

Moore’s Law good for 14nm, and probably, 10nm: Dr. Wally Rhines

May 31, 2013 Comments off

Its a pleasure to talk to Dr. Walden (Wally) C. Rhines, chairman and CEO, Mentor Graphics Corp. On his way to DAC 2013, where he will be giving a ten-minute “Visionary Talk”, he found time to speak with me. First, I asked him given that the global semiconductor industry is entering the sub-20nm era, will it continue to be ‘business as usual’ or ‘it’s going to be different this time’?

Dr. Wally Rhines.

Dr. Wally Rhines.

Dr. Rhines said: “Every generation has some differences, even though it usually seems like we’ve seen all this before. The primary change that comes with “sub-20nm” is the change in transistor structure to FinFET. This will give designers a boost toward achieving lower power. However, compared to 28nm, there will be a wafer cost penalty to pay for the additional process complexity that also includes two additional levels of resolution enhancement.”

Impact of new transistor structures
How will the new transistor structures impact on design and manufacturing?

According to him, the relatively easy impact on design is related to the simulation of a new device structure; models have already been developed and characterized but will be continuously updated until the processes are stable. More complex are the requirements for place and route and verification; support for “fin grids” and new routing and placement rules has already been implemented by the leading place and route suppliers.

He added: “Most complex is test; FinFET will require transistor-level (or “cell-aware”) design for test to detect failures, rather than just the traditional gate-level stuck-at fault models. Initial results suggest that failure to move to cell-aware ATPG will result in 500 to 1000 DPM parts being shipped to customers.

“Fortunately, “cell-aware” ATPG design tools have been available for about a year and are easily implemented with no additional EDA cost. Finally, there will be manufacturing challenges but, like all manufacturing challenges, they will be attacked, analyzed and resolved as we ramp up more volume.”

Introducing 450mm wafer handling and new lithography
Is it possible to introduce 450mm wafer handling and new lithography successfully at this point in time?

“Yes, of course,” Dr. Rhines said. “However, there are a limited number of companies that have the volume of demand to justify the investment. The wafer diameter transition decision is always a difficult one for the semiconductor manufacturing equipment companies because it is so costly and it requires a minimum volume of machines for a payback. In this case, it will happen. The base of semiconductor manufacturing equipment companies is becoming very concentrated and most of the large ones need the 450mm capability.”

What will be the impact of transistor variability and other physics issues?

As per Dr. Rhines, the impact should be significant. FinFET, for example requires controlling physical characteristics of multiple fins within a narrow range of variability. As geometries shrink, small variations become big percentages. New design challenges are always interesting for engineers but the problems will be overcome relatively quickly.
Read more…

What’s next in complex SoC verification?


Functional verification is critical in advanced SoC designs. Abey Thomas, verification competency manager, Embitel Technologies, said that over 70 percent effort in the SoC lifecycle is verification. Only one in three SoCs achieves first silicon success.

Thirty percent designs needed three or more re-spins. Three out of four designs are SoCs with one or more processors. Three out of four designs re-use existing IPs. Almost all of the embedded processor IPs have power controllability. Almost all of the SoCs have multiple asynchronous clock domains.

An average of 75 percent designs are less than 20 million gates. Significant increase in formal checking is approaching. Average number of tests performed has increased exponentially. Regression runs now span several days and weeks. Hardware emulation and FPGA prototyping is rising exponentially. There has been a significant increase in verification engineers involved. A lot of HVLs and methodologies are now available.

Verification challenges
Verification challenges include unexpected conflicts in accessing the shared resource. Complexities can arise due to an interaction between standalone systems. Next, there are arbitration priority related issues and access deadlocks, as well as exception handling priority conflicts. There are issues related to the hardware/software sequencing, and long loops and unoptimized code segments. The leakage power management and thermal management also pose problems.

There needs to be verification of performance and system power management. Multiple power regions are turned ON and OFF. Multiple clocks are also gated ON and OFF. Next, asynchronous clock domain crossing, and issues related to protocol compliance for standard interfaces. There are issues related to system stability and component reliability. Some other challenges include voltage level translators and isolation cells.

Where are we now? It is at clock gating, power gating with or without retention, multi-switching (multi-Vt) threshold transistors, multi-supply multi-voltage (MSMV), DVFS, logic optimization, thermal compensation, 2D-3D stacking, and fab process and substrate level bias control.

So, what’s needed? There must be be low power methods without impacting on performance. Careful design partitions are needed. The clock trees must be optimized. Crucial software operations need to be identified at early stages. Also, functional verification needs to be thorough.

Power hungry processes must be shortlisted. There needs to be compiler level optimization as well as hardware acceleration based optimization. There should be duplicate registers and branch prediction optimization. Finally, there should be big-little processor approach.

Present verification trends and methodologies include clock partitions, power partitions, isolation cells, level shifters and translators, serializers-deserializers, power controller, clock domain manager, and power information format – CPF or UPF. In low-power related verification, there is on power-down and on power-up. In the latter, the behavioral processes are re-enabled for evaluation.

Open source verification challenges
First, the EDA vendor decides what to support! Too many versions are released in short time frame. Object oriented concepts are used that are sometimes unfit for hardware. Modelling is sometimes done by an engineer who does not know the difference between a clock cycle and motor cycle! Next, there is too much of open source implementations without much documentation. There can be multiple, confusing implementation options as well. In some cases, no open source tools are available. There is limited tech support due to open source.

Power aware simulation steps perform register/latch recognition from RTL design. They perform identification of power elements and power control signals.They support UPF or CPF based simulation. Power reports are generated, which can be exported to a unique coverage database.

Common pitfalls include wrapper on wrapper bugs, eg. Verilog + e wrapper + SV. There is also a dependency on machine generated functional coverage goals. There may be a disconnect between the designer and verification language. There are meaningless coverage reports and defective reference models, as well as unclear and ambiguous specification definition. The proven IP can become buggy due to wrapper condition.

Tips and tricks
There needs to be some early planning tips. Certain steps need to be completed. There should be completion of code coverage targets, completion of functional coverage targets, completion of targeted checker coverage, completion of correlation between functional coverage and checker coverage list, and a complete review of all known bugs, etc.

Tips and tricks include bridging the gap between design language and verification language. There must be use of minimal wrappers to avoid wrapper level bugs. There should be a thorough review of the coverage goals. There should be better interaction between designer and verification engineers. Run using basic EDA tool versions and lower costs.

Will global semicon industry see growth in 2013?

February 2, 2013 14 comments

How will the global semiconductor industry perform in 2013? After a contrasting spell of predictions for 2012, I see no change in 2013! So, what’s the answer to the million-dollar question posed as my headline? 🙂

Global electronics industry.

Global electronics industry.

After a disappointing and challenging 2012, global semiconductor executives believe that the worst is nearly behind them, and they are making investments to position their companies for a sustained, broad-based, multi-year recovery in 2013, as per a KPMG global semiconductor survey.

On Feb. 3, the Semiconductor Industry Association (SIA) announced that worldwide semiconductor sales for 2012 reached $291.6 billion, the industry’s third-highest yearly total, ever but a decrease of 2.7 percent from the record total of $299.5 billion set in 2011. Total sales for the year narrowly beat expectations from the World Semiconductor Trade Statistics (WSTS) organization’s industry forecast.

The World Semiconductor Trade Statistics (WSTS) estimated that the global semiconductor market in 2012 will be $290 billion, down 3.2 percent from 2011, followed by a recovery of positive 4.5 percent growth to $303 billion in 2013.

The worldwide semiconductor revenue is projected to total $311 billion in 2013, a 4.5 percent increase from 2012 revenue, according to Gartner Inc. The worldwide semiconductor revenue totaled $298 billion in 2012, a 3 percent decline from 2011 revenue of $307 billion, according to preliminary results by Gartner.

The outlook for the global semiconductor industry in 2013 will likely be 7.9 percent, according to Future Horizons. It means, the industry will likely grow to $315.4 billion in 2013. The Cowan LRA foreasting model put out the following sales and year-on-year sales growth numbers for 2012 and 2013: $292.992 billion (-2.2 percent) and $309.244 billion (+5.5 percent), respectively.

Databeans expects 2013 will see a rebound, with the semiconductor industry growing by 7 percent from 2012 totals to reach $313.04 billion. IDC forecasted that the worldwide semiconductor revenues will grow 4.9 percent and reach $319 billion in 2013.

IHS iSuppli claimed that the semiconductor silicon revenue will close 2012 at $303 billion, down 2.3 percent from $310 billion in 2011. The projected decline comes in contrast to the 1.3 percent gain made last year.

IC Insights forecasted 6 percent IC unit growth for 2013 based on expectations of global GDP to rise to 3.2 percent. According to IC

Source: VLSI Research, USA.

Source: VLSI Research, USA.

Insights, in 2017, China is expected to represent 38 percent of the worldwide IC market, up from 23 percent, 10 years earlier in 2007. Does this mean the USA and Europe are loosing their sheen?

The global semiconductor industry may record only 1.5 percent growth In 2013, as per The Infornation Network. There is, however, the possibility for a snap-back in revenues for 2013, irrespective of macroeconomic factors, such as what occurred in 2010.

Over the next three years, industry analysts estimate the global industry will grow approximately 6 percent 2013-2016 CAGR, according to Somshubro Pal Choudhury, managing director, Analog Devices India Pvt. Ltd.

Late 2012, I was speaking with Dr. Wally Rhines, chairman and CEO, Mentor Graphics. He said: “After almost no growth in 2012, most of the analysts are expecting improvement in semiconductor market growth in the coming year. Currently, the analyst forecasts for the semiconductor industry in 2013 range from 4.2 percent on the low side to 16.6 percent on the high side, with most firms coming in between 6 percent and 10 percent. The average of forecasts among the major semiconductor analyst firms is approximately 8.2 percent.”

WSTS also anticipates the world market to grow 5.2 percent to $319 billion in 2014, with healthy mid single digit growth across most of geographical regions and semiconductor product categories, supported by the healthier economy of the world.

Lastly, Forbes said that 2013 will be a turning point for the global semiconductor market.
Read more…

Round-up 2012: Best of electronics, semiconductors and solar

December 31, 2012 2 comments

Friends, here is the round-up of 2012, where the best of electronics, semiconductors and solar PV are presented. Best wishes for a very happy and prosperous new year! 🙂

Also, a word on the horrendous Delhi rape that has shaken up India. I am ashamed to be a man and a part of India’s society. My family and I are extremely sorry that the brave girl is no more! May her soul rest in peace. May God deliver justice, and quickly!

DECEMBER 2012
Opportunities in turbulent PV equipment market

Global semiconductor industry outlook 2013: Jaswinder Ahuja, Cadence

Next wave of design challenges, and future growth of EDA: Dr. Wally Rhines

Global medical image sensors market to grow 64 percent by 2017

Status of power semiconductor devices industry

NOVEMBER 2012
Global solar PV industry to remain under pressure in 2013!

Dr. Wally Rhines on global semiconductor industry outlook 2013

Focus on monolithic 3D-ICs paradigm shift for semicon industry

Xilinx announces 20nm portfolio strategy

Elliptic intros world’s first commercial touchless gesturing technology!

Global semiconductor industry outlook 2013: Analog Devices

IMEC’s 450mm R&D initiative for nanoelectronics ecosystem

OCTOBER 2012
III-V high mobility semiconductors for advanced CMOS apps

Yet another electronics policy for India?

IEF 2012: Turning recession into opportunity!

Global semicon sales to drop 1.7 percent in 2012?

Virtual prototyping ready for masses

MEMS to be $21 billion market by 2017: Yole

TSMC on 450mm transition: Lithography key!

SEPTEMBER 2012
Cadence Allegro 16.6 accelerates timing closure

Dr. Wally Rhines on global EDA industry

Solarcon India 2012: Solar industry in third wave!

AUGUST 2012
Apple wins big vs. Samsung in patent war!

Can being fabless and M-SIPS take India to top?

JULY 2012
Is Europe ready for 450mm fabs?

APRIL 2012
Xilinx intros Vivado Design Suite

MARCH 2012
Cadence releases latest Encounter RTL-to-GDSII flow

WLCSP market and industrial trends

FEBRUARY 2012
Top 10 semiconductor growth drivers: Intersil

Ingredients for successful fabless Indian semiconductor industry: Dr. Wally Rhines

Tariffs will slow growth in domestic demand for PV systems: The Brattle Group

Wireless leads in global semicon spends!

JANUARY 2012
India to allow imports of low-priced Chinese solar cells? Or, is it beaten?

Virtual prototyping ready for masses

October 9, 2012 Comments off

Virtual prototyping.

Virtual prototyping.

Device volume, variety and complexity are only going to increase. Transformative technologies like virtual prototypes give organizations the tools to transcend challenges. Companies like Altera are creating competitive advantage and innovation with these solutions. Virtual prototyping is now ready for the masses.

Industry trends and challenges make virtual prototyping a must-have solution. New realities make prior adoption barriers mere myths. Virtual prototyping has become a key process for early software development and supply chain enablement. Industry trends also alter design requirements. For instance, earlier, it used to be computing and single core, which has since moved on to connectivity and multi-core.

This opens up implications for SoC development, especially, in terms of increased complexity and volume of software. There is a need to get the architecture right. No amount of downstream tools will compensate for the fundamentally wrong architecture. There is also a need to start software development earlier, in parallel with hardware design. Needless to say, hardware-software integration must be accelerated and system validation will minimize waterfall development process.

New realities of prototyping render prior barriers as mere myths. For instance, earlier, it was believed that creating a prototype is hard. IP models, TLMCentral and model creation software have come a long way, in reality. Earlier, there was a need to wait for complete prototype. Now, software can be developed incrementally and VDKs are jumpstarting the software development. Earlier, one felt the need to change software environment. In reality, the very same tools, debuggers and environment used for hardware can be used here.

Also, today, there are multiple use cases, verticals and customers of virtual prototyping. There is industry support for system-level models. The TLMCentral is an open, web-based portal that provides consolidated access to transaction-level models available across the industry, helping virtual prototype developers accelerate the creation and deployment of their prototypes for early software design.

Open and free, TLMCentral is the first industry-wide portal to aggregate available transaction-level models. It has over 1,000 models of most common IP blocks and interfaces for wireless, consumer and automotive applications. TLMCentral is supported by leading IP vendors, tool providers, service companies and universities. It also offers model developers, architects and software engineers an infrastructure for news, forums and blogs.

Integrated into the software development environment, there are popular debuggers, powerful controls and debugging information. VDK is a great starting point and for ongoing use. One can install and start using. There is no need to wait for months for a prototype. Templates, sample software and reference prototypes are available in one place. Post-silicon support and validation is provided, besides early availability for software development and testing.

Key process for earlier software development includes hardware-software integration and system validation. Semis are engaging customers earlier. The VDKs are driving tangible time-to-volume reduction. Tangible benefits of virtual prototyping include faster time to revenue, faster customer success, and faster field and ecosystem readiness.

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