Cadence Design Systems Inc. recently announced the Quantus QRC extraction solution had been certified for TSMC 16nm FinFET.
So, what’s the uniqueness about the Cadence Quantus QRC extraction solution?
KT Moore, senior group director – Product Marketing, Digital and Signoff Group, Cadence Design Systems, said: “There are several parasitic challenges that are associated with advanced node designs — especially FinFET – and it’s not just about tighter geometries and new design rules. We can bucket these challenges into two main categories: increasing complexity and modeling challenges.
“The number of process corners is exploding, and for FinFET devices specifically, there is an explosion in the parasitic coupling capacitances and resistances. This increases the design complexity and sizes. The netlist is getting bigger and bigger, and as a result, there is an increase in extraction runtimes for SoC designs and post-layout simulation and characterization runtimes for custom/analog designs.
“Our customers consistently tell us that, for advanced nodes, and especially for FinFET designs, while their extraction runtimes and time-to-signoff is increasing, their actual time-to-market is shrinking and putting an enormous amount of pressure on designers to deliver on-time tapeout. In order to address these market pressures, we have employed the massively parallel technology that was first introduced in our Tempus Timing Signoff Solution and Voltus IC Power Integrity Solution to our next-generation extraction tool, Quantus QRC Extraction Solution.
“Quantus QRC Extraction Solution enables us to deliver up to 5X better performance than competing solutions and allows scalability of up to 100s of CPUs and machines.”
Support for FinFET features
How is Quantus providing significant enhancements to support FinFET features?
Parasitic extraction is at the forefront with the introduction of any new technology node. For FinFET designs, it’s a bit more challenging due to the introduction of non-planar FinFET devices. There are more layers to be handled, more RC effects that need to be modeled and an introduction of local interconnects. There are also secondary and third order manufacturing effects that need to modeled, and all these new features have to be modeled with precise accuracy.
Performance and turnaround times are absolutely important, but if you can’t provide accuracy for these devices — especially in correlation to the foundry golden data — designers would have to over-margin their designs and leave performance on the table.
How can Cadence claim that it has the ‘tightest correlation to foundry golden data at TSMC vs. competing solutions’? And, why 16nm only?
According to Moore, the foundry partner, TSMC, asserts that Quantus QRC Extraction Solution provides best-in-class accuracy, which was referenced in the recent press announcement:
“Cadence Quantus QRC Extraction Solution successfully passed TSMC’s rigorous parasitic extraction certification requirements to achieve best-in-class accuracy against the foundry golden data for FinFET technology.”
FinFET structures present unique challenges since they are non-planar devices as opposed to its CMOS predecessor, which is a planar device. We partnered with TSMC from the very beginning to address the modeling challenges, and we’ve seen many complex shapes and structures over the year that we’ve modeled accurately.
“We’re not surprised that TSMC has recognized our best-in-class accuracy because we’re the leader in providing extraction solutions for RF designs. Cadence Quantus QRC Extraction Solution has been certified for TSMC 16nm FinFET, however, it’s important to note that we’ve been certified for all other technology nodes and our QRC techfiles are available to our customers from TSMC today.”
Future Horizons hosted the 22nd Annual International Electronics Forum, in association with IDA Ireland, on Oct. 2-4, 2013, at Dublin, Blanchardstown, Ireland. The forum was titled ‘New Markets and Opportunities in the Sub-20nm Era: Business as Usual OR It’s Different This Time.” Here are excerpts from some of the sessions. Those desirous of finding out much more should contact Malcolm Penn, CEO, Future Horizons.
The global interest in graphene research has facilitated our understanding of this rather unique material. However, the transition from the laboratory to factory has hit some challenging obstacles. In this talk I will review the current state of graphene research, focusing on the techniques which allow large scale production.
I will then discuss various aspects of our research which is based on more complex structures beyond graphene. Firstly, hexagonal boron nitride can be used as a thin dielectric material where electrons can tunnel through. Secondly, graphene-boron nitride stacks can be used as tunnelling transistor devices with promising characteristics. The same devices show interesting physics, for example, negative differential conductivity can be found at higher biases. Finally, graphene stacked with thin semiconducting layers which show promising results in photodetection.
I will conclude by speculating the fields where graphene may realistically find applications and discuss the role of the National Graphene Institute in commercializing graphene.
The key challenge for future high-end computing chips is energy efficiency in addition to traditional challenges such as yield/cost, static power, data transfer. In 2020, in order to maintain at an acceptable level the overall power consumption of all the computing systems, a gain in term of power efficiency of 1000 will be required.
To reach this objective, we need to work not only at process and technology level, but to propose disruptive multi-processor SoC architecture and to make some major evolutions on software and on the development of
applications. Some key semiconductor technologies will definitely play a key role such as: low power CMOS technologies, 3D stacking, silicon photonics and embedded non-volatile memory.
To reach this goal, the involvement of semiconductor industries will be necessary and a new ecosystem has to be put in place for establishing stronger partnerships between the semiconductor industry (IDM, foundry), IP provider, EDA provider, design house, systems and software industries.
This presentation looks at the development of the semiconductor and electronics industries from an African perspective, both globally and in Africa. Understanding the challenges that are associated with the wide scale adoption of new electronics in the African continent.
Electronics have taken over the world, and it is unthinkable in today’s modern life to operate without utilising some form of electronics on a daily basis. Similarly, in Africa the development and adoption of electronics and utilisation of semiconductors have grown exponentially. This growth on the African continent was due to the rapid uptake of mobile communications. However, this has placed in stark relief the challenges facing increased adoption of electronics in Africa, namely power consumption.
This background is central to the thesis that the industry needs to look at addressing the twin challenges of low powered and low cost devices. In Africa there are limits to the ability to frequently and consistently charge or keep electronics connected to a reliable electricity grid. Therefore, the current advances in electronics has resulted in the power industry being the biggest beneficiary of the growth in the adoption of electronics.
What needs to be done is for the industry to support and foster research on this subject in Africa, working as a global community. The challenge is creating electronics that meet these cost and power challenges. Importantly, the solution needs to be driven by the semiconductor industry not the power industry. Focus is to be placed on operating in an off-grid environment and building sustainable solutions to the continued challenge of the absence of reliable and available power.
It is my contention that Africa, as it has done with the mobile communications industry and adoption of LED lighting, will leapfrog in terms of developing and adopting low powered and cost effective electronics.
Personalized, preventive, predictive and participatory healthcare is on the horizon. Many nano-electronics research groups have entered the quest for more efficient health care in their mission statement. Electronic systems are proposed to assist in ambulatory monitoring of socalled ‘markers’ for wellness and health.
New life science tools deliver the prospect of personal diagnostics and therapy in e.g., the cardiac, neurological and oncology field. Early diagnose, detailed and fast screening technology and companioning devices to deliver the evidence of therapy effectiveness could indeed stir a – desperately needed – healthcare revolution. This talk addresses the exciting trends in ‘PPPP’ health care and relates them to an innovation roadmap in process technology, electronic circuits and system concepts.
SoC design challenges and needs are diverse. There are many diverse IP blocks. It is time consuming to verify. Picking correct IP is critically important.
Speaking on the TSMC Soft IP Alliance program, Dan Kochpatcharin, deputy director, TSMC said that IP sourcing priorities include is it available, Is it from trusted partners, how is the design quality, and what are the specs and cost? Some other points to note are: is an IP verified, has it been silicon proven, what has been tested and how many in production volume already?
TSMC Soft IP Alliance has 5000+ IP titles from 40+ IP vendors. The IP Alliance program has been expanding. It is leveraging on successful IP. More and more customers are concerned about PPA data of soft IP specific technology when doing system design.
The Soft IP Alliance has 16 members. The Soft-IP quality assessment TSMC 9000 is key. New soft-IP handoff kit were rolled out in Nov. 2012. Major partners have now joined to drive soft-IP quality, such as Imagination, Sonics, MIPS, etc.
TSMC Soft-IP 9000 has carried out industry first QA assessment system for RTL based IP. TSMC and IP partners co-optimize RTL/process to deliver PPA optimized IPs.
Mike Gianfagna, Atrenta, spoke on the implementing program with Atrenta IP kit. Atrenta’s SpyGlass is a systematic approach to soft IP quality.
If you look at what’s needed for IP assessment, there are factors such as right abstraction levels must be supported, and soft IP is delivered as generators, RTL or gates; the biggest need is here. The IP must be comprehensive, easy to use, objective and quantifiable, actionable, and dynamic and scalable. Atrenta and TSMC announced SpyGlass IP kit 2.0 in October 2012
What does the IP kit check? Many items that would impact the integration/debug time and chip function were found and fixed. Soft IP qualification can be automated. It results in higher quality deliverables. All soft IP can be improved. Primary beneficiaries are chip integrators.
John Bainbridge, Sonics, spoke on the practical results of program participation. Sonics is a leader in system IP for SoCs. It enables designers to integrate any IP from anywhere, anytime.
Sonics helps leading SoC vendors solve some of the most difficult challenges in SoC design. These can be IP integration, high frequency, memory throughput, security, physical design, power management, development costs, and time-to-market. Sonics is a lead beta partner for TSMC Soft IP 2.0 kit program. It has worked closely with Atrenta and TSMC to ensure a seamless design flow.
Milpitas, USA-based Sonics Inc. participated in TSMC’s Soft IP Alliance 2.0 beta program. Driving high quality soft IP eases customer integration and expedites time-to-market.
Sonic’s role in TSMC beta program
Speaking on the beta program and Sonics’ role, Frank Ferro, director of Product Marketing, Sonics, said: “TSMC’s Soft IP kit 2.0 beta program is part of TSMC’s Open Innovation Platform program that creates a complete ecosystem for customers with the overall goal of shortening design time. This is done by providing a large catalog of partner provided IP that is silicon-verified and production-proven.
For vendors like Sonics, TSMC has extended this ecosystem to include Soft-IP (IP not designed for a specific process, but delivered as RTL). The program allows Soft-IP partners to access and leverage TSMC’s process technologies to optimize power, performance and area for their IP.
IP cores are checked through TSMC’s foundry checklist to ensure the customers have optimized design results with fast IP integration built into their design. This flow also facilitates easy IP reuse for subsequent designs. The soft IP Kit beta 2.0 program is an extension of the current program through implementing additional quality checks, improving results and making the flow easier for customers.
There are several advantages to Sonics as a participant in this program. First, customers of TSMC will have access to Sonics IP through TSMC’s IP library. Given TSMC’s strong market share, this will allow Sonics IP to be visible to a large customer base. In addition, TSMC’s customers will feel securing using Sonics IP because they know that it has been put through a rigorous series of IP checks that meet the highest quality standards. It also allows Sonics early access to TSMC’s process libraries, allowing Sonics to optimize performance and area for each IP product.
So, what can the TSMC’s Soft IP Kit 2.0 do? How does Sonics enhance its capabilities? The Soft IP Kit 2.0 provides a specific RTL design flow methodology and hand-off which includes: lint (RTL coding consistency), clock domain crossings (CDC), power (CPF/UPF), physical design (routing congestion), design for test (DFT), constraints and documentation.
Using this flow enhances Sonics IP quality and reliability because many RTL errors can be caught at an early stage. As mentioned above, this flow ensures lowest power and best performance of the IP for a given process node.
Atrenta SpyGlass improves packaging
There is a role played by Atrenta SpyGlass. According to Ferro, Atrenta SpyGlass is the tool used to run all the tests. The flow was developed to TSMC’s standards and implemented by Atrenta. Given Sonics strong relationship with TSMC and Atrenta, we were invited to be a beta partner using our IP to test the new flow. A number of companies do participate in the program, although only Sonics has announced participation in the beta 2.0 program to date.
This tie up with Atrenta will likely improve IP packaging. As part of the overall flow, the final step, after all basic and advanced IP checks, is IP packaging. This step includes providing the IP with information on the design intent, set-up and analysis reports. Again, this is done using the SpyGlass tool from Atrenta.
This IP packaging was available to customers in the past via the Soft IP 1.0 program. The attraction of this type of IP packaging is a result of the growing number of IP cores being integrated into complex SoCs. As the number of third party IP grew, the need for a better, broader methodology was developed.
TSMC unveiled its schedule for 450mm mass production at the recently held SEMICON Taiwan 2012 450mm Supply Chain Forum. Focusing on lithography as the key, Dr. C.S. Yoo, senior director of the 450mm program at TSMC, noted that IC makers and equipment suppliers should fully leverage the G450C. They need to work and innovate to make the 450mm transition a great success.
TSMC has always been in the relentless pursuit of technology innovation. It has been part of all of the computing waves that have driven the market growth. Right now, mobile computing is the leading market driver. TSMC has been helping the industry produce comprehensive, powerful mobile computing devices.
The future growth drivers and trends include mobile computing, cloud computing and smart devices. However, technical and economic challenges also lie ahead. TSMC has been pushing the lithography roadmap. 28nm is said to be the limit of conventional single-patterning lithography. TSMC has innovations to extend immersion to 20nm. The next-generation lithography (NGL) is being preferred beyond 20nm. Also, EUV and multiple-e-beam concept and feasibility has been proven. The more than 10x throughput gap requires collaborative innovation and funding.
TSMC continues to invest in R&D for transistor architecture trends. There is increasing technology complexity, as reflected by mask layers increase. The technology shrink also leads to design complexity.
There are challenges such as intrinsic wafer cost parity and uncertain technology migration ROI. TSMC’s mission is to be the trusted technology and capacity provider for the global logic IC industry for years to come. TSMC already has capacity leadership. TSMC’s total 12″ cleanroom space will equal more than 32 World Cup football fields by the end of this year..
TSMC customers’ expectations include the offer of leading-edge technology, continue to expand capacity, enable faster time to market, faster technology ramp up, faster manufacturing cycle times, and lower cost /die. To bridge the cost and productivity gap, TSMC no longer maintains cost/transistor trend by 2018 due to the slowing pace of technology shrink, and increasing technology complexity.
IC Insights recently released the 1H-11 top 20 semicon sales leaders. No surprises here, with Intel, Samsung, TSMC, TI and Toshiba as the top five leaders in that order. In all, 10 of the top 20 suppliers outperformed the total global semiconductor industry 1H11/1H10 growth rate of 4 percent.
The fabless companies — notably, Qualcomm, Broadcom, and so on, have registered positive growths. However, if you really look carefully, a lot of the companies thereafter have registered negative growth for the period 1H-11 over 1H-10.
What’s surprising to notice is the fact that at least seven companies — Renesas, Hynix, Micron, AMD, Infineon, Elpida and NXP have registered negative growth! This, during a period when the semiconductor industry was said to be on the rebound? Whatever the reasons, they are all in the red!
Now, we are not spent from discussing an industry turnaround, which is perhaps there! Also, the forecast for 2H-11 isn’t something to go overboard. IC Insights expects the 2H11/1H11 semiconductor market to grow only 6 percent, that is, a full-year 2011 semiconductor industry growth rate of 5 percent.
Closer to home, as usual, there are no Indian firms in the global top 20 list. As things stand, they may not even make it to the list, at least, for quite a while. One hopes that this situation somehow changes. Wonder, how did the India Semiconductor Association (ISA)-Frost & Sullivan study come up with a figure of 28.3 percent growth in 2010! Perhaps, I am mistaken in my calculations somewhere!!
This is a summary by Malcolm Penn, CEO, Future Horizons. For those who wish to know more, please get in touch with me or Future Horizons.
December’s WSTS results were as boring as they were predictable, with no serious data revisions (thankfully) and the results right where we expected. December’s year-on-year IC unit growth was 8.9 percent that, with the 3.5 percent growth (yes GROWTH) in ASPs, yielded a respectable double-digit value growthof 12.8 percent. And this, on the back of a weak Q4 memory market that saw ASPs fall 13.1 percent vs Q3-10!
The yearly growth vs 2009 weighed in at 31.8 percent, hitting $298.3 billion, just shy of the elusive $300 billion threshold. The market is right where we said it would be at our recent 2011 Forecast seminar; we reiterate our position that 2011 will be a good year for the industry. Choppy first-half waters for sure, but watch out for a whopping 2H-11 ricochet.
Connectors are up as well
It is not just semiconductors that are off to a good start. The connector industry is tight as a drum too. Orders in December 2010 were up 13.3 percent versus December 2009, with full year orders up 29.3 percent on 2009, down sequentially 11.1 percent from November 2010. The comparable data for sales was plus 18.7percent, plus 28.4 and minus 13.7 percent.
The December connector book-to-bill ratio was 1.01, unchanged from November. This industry still publishes orders and book-to-bill data by the way, unlike the chip industry which very foolishly stopped publishing this several years ago. All this in the seasonally slow first quarter of the month, yet few people believe there is a supply problem in prospect. Just as this time last year, industry denial is rampant, way beyond reasonable caution and ignoring the underlying trends.
Strong demand for mobile, server and graphics DRAM
We estimate that the worldwide growth rate for PCs in 2011 will be a healthy 10 percent, with 3.9GB the average DRAM content per box. New capacity and die shrinks are putting near-term pressure on over-supply and pricing but there are now move afoot from Elpida and others to start raising prices.
Where they can, to gain a price advantage, DRAM vendors are actively adjusting their supply in favour of mobile from commodity DRAM, given the current strong demand in the smartphone and tablet PC markets, with a 1GB per box average DRAM content.
Server demand continues to be the other star segment, not just in unit demand but in content per box as well, estimated to average around 30GB in 2011. This will drive a 50 to 60 percent increase in server DRAM demand. Finally in graphics demand for specialty DRAM is also very strong, driven by the rapid take off of3D-TV and continuing strong growth in Blue-Ray DVD.
The overall DRAM industry is thus gradually diversifying from manufacturing mainly commodity DRAM to diversified products such as mobile DRAM, serverbasis DRAM, specialty DRAM and graphic memory.DRAM vendors however are faring mixed fortunes, with Elpida and Hynix having the worst net cash positions with barely enough cash to cover their short-term debt.
The Taiwanese vendors find themselves stuck in a technology trap, unable to invest in the immersion technology needed to break through the 5*nm node, meaning that in the absence of a good market uptick to improve cash flow and profits, a shake out in the DRAM supply base seems unavoidable.