Posts Tagged ‘32nm’

AMD’s roadmap 2009 provides lots of answers… now, to deliver!

November 14, 2008 Comments off

AMD’s roadmap 2009, or guidance, presented during its 2008 Financial Analyst Day on Nov. 13th, provided a lot of answers to several of the questions it had been facing. Also, AMD did something Intel hasn’t! It did not revise the Q4 guidance!! During a webcast, AMD CFO, Bob Rivet, said he would offer an update to the company’s earnings outlook in the first week of December. Also, one of AMD’s announcements, the Yukon, is definitely not going to take on Intel’s Atom, and should be priced higher.

Kicking of proceedings, Dirk Meyer, President and CEO, talked about a complete AMD & Foundry Company realignment, which includes executing key technology transitions. These include: deliver 2nd wave of 45nm products and platforms — including chipsets; transition to 40nm graphics products; finalize 32nm designs for 2010 production. Also, deliver, market and sell platforms; and continue operational excellence.

Later, during the Q&A session, when asked about the validity of AMD’s cross-license for patents with Intel, Meyer said there was no legal issue. AMD’s agreement with Intel allows AMD subsidiaries to be licensed. The Foundry Company, 43.5 percent owned by AMD, qualifies as a subsidiary, as defined, as per the agreement with Intel.

Asset Smart strategy
According to Rivet, who spoke last during the Webcast, it has been a tough operating environment. However, AMD launched Asset Smart; achieved operating profitability in Q3-08 and is now making progress toward $1.5B operating income breakeven by early ‘09. It also has a richer MPU product mix and the first 45nm product has been launched. Graphics has returned to operating profitability. AMD has already divested its DTV business and plans to sell handheld.

Asset Smart manufacturing strategy
* Strategic commitment from Mubadala
* The Foundry Company plans multi-billion dollar build-out of leading edge fabs in Dresden and Upstate New York
* Expanded IBM partnership delivering leading-edge bulk and SOI process technology

Stronger financial structure
* ~$1B new cash investment
* ~$1.2B debt assumed by The Foundry Company
* Future fab capital expenditures optional
* Reduced process technology R&D costs
* Improved free cash flow by elimination of required fabrication capital expenditures offset somewhat by wafers purchased for cash (foundry model)
* Leaner and more variable business model, with a lower breakeven point of ~$1.5B

The Foundry Company
Doug Grose, Senior VP, Manufacturing & Supply Chain Management and Incoming CEO, The Foundry Company, highlighted AMD’s 2009 manufacturing priorities. These are: transition to best-in-class foundry model; complete conversion to 45nm production; and successful 32nm technology development.

This October 7, AMD and the Advanced Technology Investment Co. announced their intention to create a new global enterprise, The Foundry Company, to address the growing global demand for independent, leading-edge semiconductor manufacturing. This announcement was the lynchpin of AMD’s Asset Smart plan, and a key initiative designed to enable the company to achieve sustainable profitability.

At the 2008 AMD Financial Analyst Day event, AMD provided more details on what its manufacturing operations will look like once the spin-out of The Foundry Company is complete.
* For the Silicon on Insulator (SOI) and bulk manufacturing processes needed to build AMD CPUs and APUs, The Foundry Company plans to offer AMD 65nm, 45nm and 32nm manufacturing capabilities at:
– Fab 36 (Dresden)
– Fab 38 (Dresden)
– Fab 4x (Saratoga County, NY)
* For the bulk manufacturing processes AMD uses to manufacture its chipsets and GPUs, AMD plans to have access to 55nm, 40nm and 32nm manufacturing capabilities at:
– TSMC/UMC (Taiwan)
– Fab 38 (Dresden)
– Fab 4x (Saratoga County, NY)
* The Foundry Company also provided an update on its progress towards moving to a new 32nm manufacturing process for bulk and SOI production. The company confirmed that it will complete 32nm test chips in Dresden by the end of year, and is on schedule to successfully incorporate High-k Metal Gate within this process node. 32nm technology development will ramp in late 2009 in preparation for 1H 2010 volume production.

Platforms for ultraportable notebooks and mini-notebooks
There has been lot of interest in ultraportable notebooks and mini-notebooks, owing to their small form factor and lightweight profile. AMD also announced new platforms aimed at serving these markets.
* AMD introduced two ultraportable notebook platforms — Congo and Yukon. Congo is based on the dual-core Conesus CPU with the RS780M and SB710 chipset. Yukon is based on a single-core CPU with the RS690E and SB600 chipset. While targeted at the ultra-portable market, these platforms are designed to address a portion of mini-notebook market, especially at the dissatisfied users of limited Internet experience of mini-notebooks. Yukon is planned to be available in 1H09 followed by Congo in 2H09.
* AMD announced the 2010 ultraportable notebook platform code named Nile. It will feature dual-core Geneva CPU utilizing DDR3.
* In 2011, AMD plans to introduce the dual-core Ontario APU for ultraportable and mini-notebook platforms.

Server platforms
* Fiorano, the first AMD platform to combine AMD server processors and chipsets. It is on schedule for mid-2009 introduction based on planned release of the AMD SR5690 chipset. Fiorano will likely support Shanghai and the upcoming six-core Istanbul processor in 2H09.
* AMD’s next-generation, DDR3-based server platform, Maranello, remains on track for introduction in 1H10.

Desktop platforms
* Dragon is set to launch in Q1 2009 and feature AMD’s upcoming 45nm AMD Phenom II X4 quad-core processors, codenamed Deneb.
* Kodiak is scheduled to enhance AMD Business Class platforms in 2H09.
* Pisces mainstream desktop platform will debut in 2H09.
* Maui is its new home theater platform planned for launch in Q408.

There you have it! Everyone wants the global semiconductor industry to be humming and chirping! It would be great if AMD delivers on its promise and hopefully, becomes profitable all over again as well.

For those keen, PDF files of all of AMD’s presentations can be downloaded from its web site.

Intel showcases world’s first Moorestown platform at IDF Taiwan

October 24, 2008 Comments off

Intel showcased the world’s first Moorestown platform at the recently held Intel Developer Forum in Taipei, Taiwan.

In his opening keynote on Day 1 at the IDF: Innovating a New Reality, Anand Chandrasekher, Senior Vice President, General Manager, Ultra Mobility Group, Intel Corp., said: “It is a world in transformation. There have been 3 billion new entrants in the global economy. The resilience of the global economy has been incredibly strong. The Internet has equalized the level-playing field.”

He added how technology innovation and strong industry collaboration have driven the digital economy over the past 40 years, and the universal impact that the Internet and mobile Web has had in people’s lives.

“Technology innovation is the catalyst for new user experiences, industry collaborations and business models that together will shape the next 40 years,” said Chandrasekher. “As the next billion people connect to and experience the Internet, significant opportunities lie in the power of technology and the development of purpose-built devices that deliver more targeted computing needs and experiences.”

Asia’s growing might
Chandrasekher added: “IT is more important today, than it has ever been over the last 20 years. Asia has been playing a dramatic role.” In fact, in 2007, Asia accounted for over 25 percent of Intel’s revenue. “Look at the PC companies. ASUS, Acer, Lenovo, etc., are now in the top 10. The number of PCs in China exceeds the US’s population. There are more handsets in Taiwan than the people in Taiwan,” he highlighted. As for the Internet, Asia is now the fastest growing region online.

The foundation of the Internet is silicon, whose foundation is the Intel architecture (IA). Chandrasekher said: “It is the ecosystem for growth, tomorrow. If you don’t have the tools to drive the Internet ecosystem, you have fallen behind.” As a comparison, during 1971, the 4004 processor had 2,250 transistors. In 2008, the Core 2 Quad processor has 820 million transistors. It also consumes 93 percent less power. “Process is one piece of the foundation. Architecture is the other,” he added.

Welcome Nehalem!
Chandrasekher next focused on the upcoming Nehalem microarchitecture, which, he said, has an extremely energy efficient design. “We have introduced the turbo mode and dynamic power management. We have hyper-threading technology as well.” He pointed out that Intel has a 32nm version of the Nehalem, which should be out soon. “There has been a huge performance increase, almost 2X, with Nehalem.”

According to him, developers love parallel programming and the Intel IA. “We are giving the Larabee. It increases the throughput performance and the programmability.”

World’s first working Moorestown platform
The event’s showstopper: a live video from a Moorestown lab in Taiwan, which also demonstrated the world’s first working Moorestown platform! The Moorestown platform is scheduled for 2009-2010 timeframe.

Moorestown comprises of an SoC, codenamed “Lincroft,” which integrates the 45nm processor, graphics, memory controller and video encode/decode onto a single chip and an I/O hub codenamed “Langwell”, which supports a range of I/O ports to connect with wireless, storage, and display components in addition to incorporating several board level functions.

Chandrasekher showed off a ”Moorestown” wafer to the delegates.

In the next blog, I will introduce you to the Father of the Atom!

Mentor Graphics: DFM is where all the value is!

September 28, 2008 Comments off

As promised, here is the concluding part of my discussion with Joseph Sawicki, vice president & GM, Design to Silicon Division, Mentor Graphics.

We went over the design for manufacturing (DFM) challenges and how yield can be improved. He also touched upon the design challenges in 45nm and 32nm, respectively.

Given that the semiconductor industry does speak a lot about DFM, what steps are being taken to improve on the overall yield?

According to Sawicki, in the VLSI microchip era, yields started at 60-70 percent, and so DFM wasn’t required. However, in the nanochip era, DFM is where all the value is. [VLSI Research.]

Joseph Sawicki, vice president & GM, Design to Silicon Division, Mentor GraphicsHe added that at smaller geometries, manufacturing variability has a much greater impact on timing, power dissipation, and signal integrity. Traditional guardbanding is no longer sufficient to guarantee competitive performance at acceptable yields, and excessive design margins erase the advantages sought by going to the next node in the first place.

Moving to advanced technologies without dealing effectively with manufacturing variability can actually put a design at a competitive disadvantage due to low parametric yield.

“Successful IC implementation requires a detailed understanding of how variability affects both functional and parametric yield. Customers need a manufacturing-aware engineering approach that extends across the entire physical implementation life cycle, starting with cell library development and extending through place and route, physical verification, layout optimization, mask preparation, testing, and failure analysis.

“They need a design flow that helps them “co-optimize” for both performance and yield simultaneously, based on accurate models of manufacturing process variability. The ability to do this quickly and effectively can give IC designers a powerful competitive advantage,” Sawicki said.

There is no silver bullet! It takes a broad-based, well-integrated approach to have a significant and consistent impact on manufacturability.

According to him, Mentor Graphics provides a complete manufacturing-aware design-to-silicon solution addressing random particle effects, small-scale device and interconnect interactions, lithographic distortions and process window variations, and thickness variations resulting from chemical-mechanical polishing (CMP) and variable film deposition and etch rates.

“Our tools incorporate comprehensive, highly-accurate models that have been tuned and verified for specific manufacturing environments, and address every stage of the digital IC implementation life cycle,” he added.

So, how is Mentor handling 45nm and 32nm design challenges?

Sawicki added: “Advanced process nodes present challenges at every stage of IC implementation, from place-and-route, through physical verification, layout enhancement, testing and yield analysis. Mentor has a complete design-to-silicon flow that addresses the critical challenges of IC implementation at every stage.”

Top 10 global semicon predictions — where are we today

May 17, 2008 Comments off

It is always interesting to write semicon blogs! Lots of people come up to me with their own comments, insights, requests, etc. One such request came from a friend in Taiwan, who’s involved with the semiconductor industry.

I was asked forthrightly what I thought of the top 10 global predictions, which I had blogged/written about some time back late last year.

Top 10 semicon predictions
For those who came in late, here are the 10 global predictions on semiconductors made at that time (late December 2007.

1. Semiconductor firms may have to face a recession year in an election year.
2. DRAM market looks weak in 2008.
3. NAND market will remain hot.
4. Power will remain a major issue.
5. EDA has to catch up.
6. Need to solve embedded (software crisis?) dilemma.
7. Consolidation in the fab space.
8. Capital equipment guys will continue to move to other market.
9. Spend on capital equipment to drop.
10. Mini fabs in developing countries.

Well, lot of water has flowed since those predictions were made. Let’s see how things stand, as of now. The updated predictions would look something like these:

1. There have been signs of recession, but the industry has faced it well, so far. In fact, Future Horizons feels that if there is going to be a global economic recession, the chip industry (but not all companies) is in the best shape possible to weather the ensuing storm.

2. Memory market is changing slightly as well, though people are very cautious. According to Converge, memory market prices appear to be stabilizing. iSuppli has predicted a poor year for DRAM though!

3. NAND Flash could show some recovery later this year. Yes, Q1-08 QoQ sales seems to have slipped, but the market remains hopeful of a recovery. Even iSuppli warned of NAND Flash slowdown in 2008, while Apple slashed its NAND order forecast significantly for 2008! Keep those fingers crossed!!

4. Power remains a big issue, and will continue to be so. This will remain as we move up newer technology process nodes.

5. EDA is seemingly catching up with 45nm designs. Magma, Synopsys, and the other leading EDA vendors are said to be playing big roles in 45nm designs.

6. Fabless companies are gaining in strength. No doubt about it! The 2007 semicon rankings show that. Also, Qualcomm is now the leader in the top wireless semicon suppliers, displacing Texas Instruments.

7. There have been consilidations (or long term alliances) in: a) fab space b) DRAM space. In the fab space, Intel, Samsung and TSMC have combined to go with 450mm wafer fab line by 2012. And in the DRAM space, there have been new camps, such as Elpida-Qimonda, and Nanya-Micron partnering to take on Samsung. With the global semiconductor market seeing steady decline in growth rate, which would continue, look forward to more consolidations.

8. Investments in photovoltaics (PV) have eased the pressure on capital equipment makers and spend somewhat. In fact, 2007 will be remembered as the year when the PV industry emerged as a key opportunity for subsystems suppliers and provided a timely boost in sales for those companies actively addressing this market. Perhaps, here lies an opportunity for India.

9. Mini fabs — these are yet to happen; so far talks only. In India, a single silicon wafer fab has yet to start functioning, even though it has been quite a while since the semicon policy was announced. Conversely, some feel that India should focus on design, rather than go after something as mature as having wafer fabs. However, several solar fabs — from Moser Baer, Videocon, Reliance, etc., are quite likely.

10. Moving to 45nm from 32nm is posing more design challenges than thought. This is largely due to the use of new materials. Well, 45nm will herald a totally different structure — metal gate/high-k/thin FET/deep trench design, etc. It will herald a new way of system design as well.

Now, I am not a semicon expert by any long distance, and welcome comments, suggestions, improvements from you all.

Semicon to grow 12pc in 2008: Future Horizons

May 14, 2008 Comments off

If there is going to be a global economic recession, the chip industry (but not all companies) is in the best shape possible to weather the ensuing storm!

According to Malcom Penn, CEO, Future Horizons, we are dealing with a semiconductor industry in ‘deep trauma.’ He was delivering the company’s forecast at the recently held International Electronics Forum (IEF) 2008 in Dubai, predicting a 12 percent growth this year despite signs of a wobbling US economy.

Is there a need to get back to the industry basics? “Semiconductors are a peculiar business; the only sane strategy is to bet the company regularly,” once remarked Dr Gordon Moore.

Penn noted that the current industry status is somewhat confused and uncertain. Short-term issues are dominating the agenda.

Longer-term structural trends are unclear. The traditional IDMs are currently going through a mid-life ‘new business model’ identity crisis, and the start-ups are struggling to even reach critical mass! And all of this has been happening amidst intense economic uncertainty

“Now is the time for strong nerves and determination,” Penn said. According to him, the underlying industry fundamentals are sound and there is no end in sight to the ‘make-lunch-or-be-lunch’ ethos.

The emerging economies like India and China have so far been less affected by the financial market’s turbulence. In fact, the emerging and developing economies were shifting the global growth dynamics.

Chip industry in best possible shape
A forecast health warning is: IF the global economy collapses, it will take the chip market with it. However, Future Horizons feels that if there is going to be a global economic recession, the chip industry (but not all companies) is in the best shape possible to weather the ensuing storm.

The ASPs are an enigma wrapped up in riddle. The course of ASPs (like love) never runs smooth. Wobbles happen! ASPs are also the perennial (and least understood) industry wild card. ASPs are generally driven by new IC designs, and that takes time (sometimes three to four years). Post-2001, value recovery lost one generation (130nm impact). The ASP recovery ‘wobbled’ in 2007 (memory and MPU price wars). Barring a recession, Future Horizons forecasts that ASPs will recover in 2008 (it has already started).

12 percent growth likely
Future Horizons’ 2008 forecast summary and assumptions (as of May 2008) are — ‘12 percent’ growth — ’10 percent’ units / ‘2 percent’ ASP. There may be no global economic recession, although US/UK/Eurozone might wobble — which they are! No significant inventory correction will probably take place, but there are always Q4>Q1 adjustments, and there’s nothing special about that either.

There could be lower fab capacity expansion due to 2007/2008 capex slowdown, which is inevitable and irreversible. There is also a possibility of a more stable memory price erosion — which means, back to the learning vs. bleeding curve, and prices have since hardened. If the global economy holds, the 2H-08 growth will likely be strong. This, if the capacity, ASP and units are all pulling together, which is said to be happening.

Therefore, Penn feels it is too early to call for a (major) downward revision. Q1 08 was a lot stronger than conventional wisdom feared.

“That’s the rational analysis, but semiconductors aren’t rational. It could just as easily be another single digit growth year,” Penn added.

Danger signs to watch out for
So, what are the danger signs one should watch out for? These would be capacity — it is hard to see how this can spoil 2008, provided unit growth holds up, but there is a need to watch capex. Another factor is demand — the current IC unit demand is sustainable provided the economy holds up, so there is a need to watch the inventory.

Next comes the economy! The current outlook continues to be uncertain with risks all on the downside. ASPs are the key to recovery, but always the first line of defence. ASPs could still derail 2008, but the trends are encouraging.

What’s driving the market?
In semiconductor 7.0 — or the 7th decade of the transistor revolution, the same things, as always, are driving the market. These are: technology, legislation — energy saving/conservation and structural — the relentless analog to digital conversion. All of these are combining to do what the chip industry does best — enabling something that was previously impossible. Penn contends, “This industry has nowhere near run out of steam!”

New applications continue to drive the market, with automotive, industrial and medical, mobile phones, and PCs and servers, dominating. The PC market is dominating, but going nowhere fast. Mobile phones have become more interesting, but have conflicting priorities. The challenges are: how to protect the existing cost structure and subscriber base and how to add useful and affordable value-add services! Evidently, “chipset suppliers love the high end, market loves the low end.”

There is definitely an increasing automotive semiconductor content. A solid annual growth has been prediced (CAGR 2006-11) for vehicles — 5.5 percent, systems — 11.5 percent, and semiconductors — 13.3 percent. Some other new areas are motor control and energy, as well as lighting and photovoltaic, besides medical electronics. Robotics is yet another interesting area.

Key industry issues
It is clear that more chips per wafer equals less cost per chip and more transistors per die equals more functionality. Several billion transistors gives phenomenal design flexibility as well. Considering total ICs and MOS ICs, in the MOS capacity build out by technology node, there has been no change in volume ramp profile despite the hype.

As for the evolution of the technology node, definitely, 45nm is a revolutionary step from 65nm. In all likelihood, 32nm will be a natural evolutionary. However, Penn cautioned that 22nm would be another ‘difficult’ transition!

There is no doubt that 65nm will be tomorrow’s leading-edge workhorse, having the same basic Si gate/SiO2/MOSFET structure. Nevertheless, 45nm will herald a totally different structure — metal gate/high-k/thin FET/deep trench design, etc. Also, 45nm will herald a new way of system design.

Is fabless right?
Is Fablite a valid option? While there is nothing wrong with being fabless, people are just not sure whether the best starting point is being an IDM. Teamwork has to be perfectly orchestrated as competition is tough.

As for the market share dynamics, the top 10 companies (IDMs) have been losing share. Fabless share has been growing, but it is still relatively small.

Coming to the realities of the foundry market, TSMC’s lead is now unassailable. Were it an IDM, it would be No. 2, challenging Intel and passing Samsung. Moving more into design looks inevitable.

Finally, execution, and not technology, is everything! Execution has and will continue to make the difference. Applications (software) will play the role of the key differentiator as well, and it has value. Design is the means to an end, and not the end.

From the chip industry’s perspective, the electronics market was traditionally Japan, North America and Western Europe. It now encompasses the entire Asian rim, China, Eastern Europe and India. Far from maturing, the chip industry itself is still in its volatile, high-growth phase, with at least a further 20 years of strong growth in prospect. Penn said, “The underlying growth drivers for chips has never been better.”

Back to basics
We started with the need to get back to industry basics. We end in the same way! Stick to basics like:

* Don’t invest in low cost areas just because they are cheap — they have a habit of becoming high cost tomorrow, plus the hidden extras.
* Don’t make outsourcing decisions just because they are easy — especially if there’s no way back.
* Don’t make strategic cut-backs just to trim the bottom line — some decisions, e.g., R&D, take a long time to impact, then it’s too late.
* Stop looking for high volume/high value market niches — they don’t exist, need to learn how to compete
* Do show strong leadership
* Do have a long-term plan and stick with it — even if it negatively impacts ‘the next quarter’ balance sheet
* Do show a commitment and determination to succeed
* Do stay focused and resistant to external meddling
* Do execute ruthlessly — this is the key competitive differentiator)
* Do … just do it with passion — it’s the passion that makes the difference

R&D innovation: nano-scale to tera-scale

January 29, 2008 Comments off

Justin Rattner, VP and Senior Fellow CTO, Intel Corp., while speaking at the recently held CXO Forum organized by the India Semiconductor Association (ISA), highlighted the various innovations Intel has created over the years and continues to do so.

There are some hurdles to innovation. For instance, success brings conservatism and then, there is the curse of high-volume manufacturing. It led to Andy Grove’s famous statement: “Only the paranoid survive”. Obviously, massive inertia and innovation do not blend. Rattner mentioned certain external hurdles, especially, anti-Innovation policies and standards that hamper innovation.

Moore’s Law drives innovation
Moore’s Law has been driving innovation at Intel. These have been in the form of high-K metal gate transistors at 45nm — the first new transistor architecture in 35 years! There’s more, in form of phase change memory (PCM) below 45nm, non-planar tri-gate transistor beyond 32nm, and carbon nanotube transistor

Some recent multi-disciplinary innovations include 45nm Core 2 Duo, Nehalem uArch, power management, quad core through package technology, Silverthorne/LPIA, USB/PCI Express, vPro, and WiMAX and 802.11n, respectively. Intel has made sustained Advances in silicon technology. In 2007, it developed 32nm SRAM with 1.9 billion transistors, with 32nm slated for 2009.

Sustained advances in micro-architecture include Intel Core — new microarchitecture 65nm (2006), Penryn compaction/derivative at 45nm (2007), Nehalem — new microarchitecture 45nm (2008), Westmere compaction/derivative 32nm (2009), and Sandy Bridge new microarchitecture 32nm (2010). “This shows our sustained microprocessor leadership,” added Rattner.

There are plans to further reinvigorate Intel architecture — by high throughput computing, IA programmability, ease of scaling for software, array of enhanced IA cores, and increasing teraflops of performance. Its 45nm Silverthorne is based on the Menlow platform and promises ‘Full Internet in Your Pocket.’

Intel has also made advances in integration and packaging, such as multi chip packages, Wifi + WiMAX, processor + chipsets + accelerators, 60 percent smaller CPU packages, and 100 percent lead-free technology*. By 2008, Intel is committed to having all 45nm CPUs halogen free.

Innovations in memory, communications
Intel has also made innovations in memory technology. Robson Technology, which has NAND Flash cache, has 1.5X faster application load times, has 1.5X resume from hibernate, gives 0.4W average power savings, and is used in the Santa Rosa platform.

The other innovation is solid-state drives. These are embedded in a range of devices, from handhelds to servers. Compared to HDDs, these give 1/10th the power, >10X performance, and are 1,000X more durable.

Innovations in communication technology include things like adaptive antenna and front-ends, digital CMOS radio, and reconfigurable baseband. Intel has also developed the world’s 1st TeraFLOPS supercomputer on a die. It features 80 cores, 1TFLOP at 62W, and 256 GB/s bisection.

Intel has also unleashed the era of tera. These are in the form of tera bits –- Si Photonics and tera bytes –- 3D stacked memory. The latter includes 256KB SRAM per core, 4X C4 bump density, and 3200 thru-silicon vias.

Similarly, Intel’s innovation in tera-scale software include RMS workloads, C++ for parallelism, Ct for nested data parallelism (race-free irregular parallel computation), and hardware assisted STM C transactional memory, which ensures concurrent access with no errors.

Intel has also done innovations for emerging regions. Rattner touched upon Research (at the Berkeley Lablet), which involves a long-distance WiFi solution: 6Mb/s at 100+ km. This has been tested at the Aravind Eye Hospital in Tamil Nadu. It has allowed doctor/patient videoconferences. Thirteen rural villages have been connected so far, going on to 50 villages. The impact has been tremendous — 2,500 exams per month, over 30,000 so far; cataracts, glaucoma, cornea problems have been diagnosed; and 3,000 people have had their vision restored so far.

Intel has also been a champion in innovating through collaboration. These have been in form of academic open-collaborative (pre-competitive research) — Carnegie Mellon, Berkeley, University of Washington; industrial partnerships (product differentiation) — an example being the, and consortium (ecosystem benefit) — via the ISA, Continua, Innovation Value Institute, Trusted Computing Group, etc.

Intel’s focus areas for 2008 include:
a) tera-scale computing — unleashing the next generation of applications.
b) Platform* on a chip (POC) — ‘Platform’ integration on chip with IA.
c) Trusted services — technologies for secure service opportunities.
d) Carry small, live large — context aware usage models and platforms.
e) Ultimate connectivity — connected ‘all-ways’ for future platforms.

Semicon outlook 2008: Global market likely to grow 6-11 percent amid recession fears

December 24, 2007 Comments off

While a majority of analysts at a recent panel discussion on global semiconductor outlook predicted semiconductor growth in the range of 6-11 percent during 2008, some other panelists predicted 2008 to be flat year or a year of negative growth.

There were fears of a possible recession in 2008, along with concerns surrounding consumer spend that could be hit by higher oil prices and the US mortgage crisis.

This panel discussion was organized last week by Semiconductor International, USA. Here is the full report.

Semi forecasts mixed for 2008

Amid concerns of a possible recession in the US economy in 2008, analysts at a recent Webcast hosted by Semiconductor International, were divided in their forecasts for the coming year. A majority predicted semiconductor growth to be in the range of 6-11 percent during 2008, while some others predicted 2008 to be flat year or a year of negative growth.

Anne Craib, director of Market Research, International Affairs and Finance, Semiconductor Industry Association (SIA), said the global economic situation needed to be factored in, as well as its impact on consumer demand.

She said: “Semiconductor demand is driven over 50 percent by consumer demand currently. That is something we should increasingly be aware of. Areas like gas prices and the home mortgage market are things that we previously would not have paid much attention to that we have had to take into account in our forecasting this cycle.” She was confident of the semiconductor industry reaching 7-8 percent CAGR during 2008.

Steve Szirom, President,, added that many economists were predicting recession in 2008. He said: “The demand-supply balance should be somehwat better than this year. We may have a demand driven recession.” He adopted a pessimistic view for 2008, predicting -8 percent growth.

DRAM weak, NAND bright

Gary Grandbois, principal analyst for iSuppli Corp., noted: “We have reduced our forecast to 7.5 percent for 2008 and think it might go lower than that. We think it’s going to be a negative first half. Certainly in the DRAM area, it’s looking very poor. We think it will improve in the second half, almost mirroring 2007, but giving us a far weaker year in 2008 than we’ve expected.”

Richard Gordon, Managing Vice President, Semiconductors, Gartner Dataquest Research, agreed with Grandbois, adding that DRAM would see a negative side in 2008. “Our forecast is 6 percent for 2008, and it doesn’t factor in the US recession,” he said.

While the DRAM market has been predicted to be negative next year, analysts see a positive market for NAND in 2008. New applications, such as WUSB (wireless USB), increase in cell phones, higher content in portable media players, etc., are likely to drive growth.

Commenting further on the outlook for 2008, Moshe Handelsman, President, Advanced Forecasting Inc., noted that 2007 would be the peak of current IC cycle. “From that point on, the underlying demand for semiconductors will decline and decline in 2008. We are negative about 2008,” he added.

Carl Johnson, Executive Director, Research Infrastructure, concurred that the industry had become much more global. “We now have to look at the mortgage debacle, etc. Consumers will be very tight in first half of this year.” He added, “I would say, next year’s going to be flat.”

Mike Cowan, an independent semiconductor industry analyst, said the growth would be about 8.15 percent during 2008. “The dynamics of the market and the industry will change month-to-month as well,” he quipped.

Capex likely to dip in 2008

Regarding capex in 2008, Carl Johnson of Research Infrastructure, expects the next year to be bumpy as far as capital spending is concerned. “We’re in a downturn right now. Foundries, who are investing lot more money in older process generations, and that is a function of some of the other older IDMs and fabs, are actually shutting down and saying, ‘we can go over to the foundries and process wafers for less than what we can do it on our own’. We are seeing lot of consolidation within the fab space. Mid-level players are consolidating. The customer base is clearly narrowing.”

The cost of designing some of these leading-edge devices, and getting them to market, and then following it up with another product, if you don’t want to be a one-product guy, is a real challenge. That is limiting the number of players that are going into the mega fabs. So, the field is narrowing in 65nm, and 45nm, and as we get to below 45nm, the field is going to get much, much narrower.

According to him, capital spending is likely to be down in 2008. “I am predicting 10 percent down next year. There’s also going to be a great consolidation in the devices manufacturing community, and also in the capital equipment community. We are seeing a number of M&A activities in the capital equipment business. It will also go into the supply chain business.”

Gartner’s Richard Gordon said the research firm was forecasting capex to be down by -15 percent in capex in 2008, and that includes -30 percent in the DRAM sector. He added: “Looking at the individual companies in the DRAM space, I won’t be surprised to see that go even lower. So, -15 percent in capex can get even worse as 2008 unfolds. We will see it coming back. But, it will take a while for demand to catch up with supply.”

EDA industry in catch-up mode

The EDA industry is said to be lagging behind the semiconductor industry at the moment, and is in the catch-up mode, according to Gary Smith, President, Gary Smith EDA.

Commenting on the outlook for the EDA market, Smith said the EDA industry is in a lttile unusual position. He said: “The market’s been flat for the past four years. Tools for 65nm, 45nm silicon design have also been delayed.” The R&D was not put in because of the recession. “Right now, we are in a position of lag in the market,” he added.

EDA tools cover two process generations. The industry is just starting to introduce 65nm and 45nm tools. That generation is being called the DFM generation tool. Smith said: “It is even more important to the semiconductor industry as we run into manufacturing problems that they are relying on design tools to solve, rather than on semiconductor equipment.” That’s a major shift in the market!

EDA to grow 7.8 percent in 2008

According to him, the industry is now now into a pretty good growth area. “We were 11 percent last year, 10.2 percent to come in this year. We will be a bit down next year at 7.8 percent,” he forecast. This has been attributed mainly to the EDA industry’s lag in the market. “Some are moving to 32nm. And certainly, a lot of work is being done in 45nm,” he added.

Smith noted: “The EDA industry is in the catch-up mode. We will lag them. We are expecting the downturn to really hit us in 2009. However, we are not an industry that goes negative often. No matter what you guys do, you still have to design something. So, when you go into recession, typically, the way you get out of recession is you generally design your way out!”

DFM, ESL growth drivers

Among the growth drivers is the DFM (design for manufacturing) issue, which is increasingly getting more complex. There is said to be a move to restrict the design rules that is in place now for 45nm. “We are going to see major changes in 32nm; that’ll have impact on tools,” he added.

The other issue is parallel computing that has become a major task for the EDA industry. “With signal threading, we can no longer handle designs over 100 million gates. Of course, at 45nm, you can do a 100mn gates. That rewriting process is another issue that is also slowing out down. That’s a full three-year re-write,” Smith said.

Further, EDA is also starting to move up into the ESL. The electronic-system level (ESL) is going to shift the EDA market more into the systems market, and serve less on its dependency on the semiconductor world.

New fabs in India, China

There have been a lot of announcements made regarding new fabs, especially in places such as India, China and Brazil.

Gary Grandbois at iSuppli said: “Brazil is a better example. India just announced that they are building new fabs. What we saw at the turn of the century is that the industry split into two areas — one traditional components manufacturer and second is the SoC manufacturer. Those are the companies that need leading edge fabs.”

According to him, the cost of R&D was going out of sight for process development. “We’re also seeing consolidation of research groups. We expect that come down to five consortiums or less. All companies can afford do their own process development once the basic process has been developed.”

There are going to be different types of fabs. With globalization, lot of countries may decide they want to have a fab. Brazil announced one. “You’re going to see them all over the world. The market’s going to change,” he added.

Anne Craib from the Semiconductor Industry Association said: “If you look at the cost structure, it costs over $1bn to build and operate a fab in the US. The question is where is the fab going to be located? The US companies will continue to be major players. Again, the question is: where is it going to be economically feasible? The interest is outside of the US.”

New elements likely in 32nm

On the subject of integration of MEMS, 3D, etc., Carl Johnson from Research Infrastructure said, “A very large topic with the design community is big change in computer architecture — the big change is the multicore — that’s the biggest driver now.”

Jim Feldhan, President, Semico Research Corp., noted that the industry is going to hit limits with silicon processing at some point of time. “We have to bring in new elements. In 32nm, there’ll be only a handful of companies who can push real hard there and can afford it.”

Push to 450mm fabs unlikely?

Finally, is there be going to be a push to 450mm fabs and how’s the impact going to be like?

iSuppli’s Gary Grandbois, said that curently the industry was expecting that it would need to abandon silicon in 2020. “If we don’t have any silver bullets by then, we are going to use nano stuff to augment CMOS. We don’t know what that’s going to be.”

He added: The issue is: are we going to use silicon at all in 2020? If we start developing equipment for 450mm, we’re not going to have that very soon. What they have to consider, what is the payback for that move?”

We would love to hear from you on how you see the semiconductor industry going in 2008.

Challenges for IC industry and Dr. Gargini’s lessons

July 26, 2007 Comments off

Those who were fortunate enough to attend the recently held SEMICON WEST in San Francisco had the pleasure of attending a great session on the past. present and future challenges for the IC industry by Dr. Paolo Gargini, Director of Technology Strategy at Intel.

For those who may not have the time to read this article, here’s a snippet of what Dr. Gargini had to offer. The first lesson, he said, was that, “Something right may still happen even when everything seems to be going wrong.” However, challenges that were continuously posed also needed to be addressed at the earliest, in order to keep moving forward.

Many also predicted several times that some limit would be reached – that chip development would never get below ten nanometers, or below five nanometers. However, the industry was able to produce components with a gate oxide at about 1.2 nanometers.

Later, the game changed to scaling, which led to Gargini’s second lesson – “Predictors of engineering limits have always been proven wrong by the right improvements.” Shrinking silicon technology of the 1990s kept the industry moving forward.

His third lesson was, “It would be wrong to believe that the right fundamental limits don’t exist.” The fourth lesson was, “It is wise to look for the right solutions before things start going wrong.” Dr. Gargini recalled how Intel had announced that 45nm generation was ready. That it included high-k metal gates was only disclosed this January giving Intel the time to work on yields, enhancements, reliability problems, etc.

Gargini quoted Gordon Moore as saying that introduction of high-k metal gates was the single most important innovation in semiconductor manufacturing of the last 40 years!

Interestingly, a few weeks ago, the PULLNANO Consortium announced breakthrough results for 32nm/22nm. Among other things, the PULLNANO consortium has fabricated a functional SRAM using innovative MOS transistors whose device architecture differs significantly from that of transistors used in 45nm technology node.

These transistors are built using a low power consumption approach based on Fully Depleted Silicon On Insulator (FDSOI), coupled with a gate stack composed of a high-K gate dielectric and a single metal electrode stack. This is said to be the first time that such a compact SRAM cell has been fabricated using FDSOI, high-k dielectric and metal gate together.

Coming back to Dr. Gargini, his fifth lesson was, “It would be wrong to delay taking action and not do the right thing at the right time.” According to him, there was a need for re-examining the opportunities for reviewing “old” theories and techniques that didn’t work on silicon.

Paradigm shift indeed in semicon

July 11, 2007 Comments off

Going through an article written by Dr. Wolfgang Ziebart, Member of the Management Board, President and CEO, Infineon Technologies, in Financial Times Deutschland, one cannot help but appreciate the great paradigm shift that has indeed taken place in the semiconductor industry.

The article titled: A paradigm shift in the semiconductor industry: Could this be the end of Moore’s Law? focuses on how changing technologies are indeed making life difficult for most market players to keep pace with all those changes.

The technical possibilities for shrinking chips have far from reached their limits at 65nm. There are preparations already on for 45nm and development work for 32nm has already started!

When PULLNANO announced breakthrough results for 32/22nm, did it surprise many? The PULLNANO consortium has fabricated a functional SRAM using innovative MOS transistors whose device architecture differs significantly from that of transistors used in 45nm technology node.

It talks about a compact SRAM cell that has been fabricated using FDSOI (Fully Depleted Silicon On Insulator), high-k dielectric and metal gate all together.

PULLNANO has demonstrated that the material and integration schemes used in 45nm generation can be modified to provide a robust solution at 32nm. It has also proposed an innovative new architecture that could provide even higher performance at 32nm and 22nm, using the so-called ‘air gap’ technique.

I do remember Dr Pradip Dutta of Synopsys India telling me about two months ago about 32nm, during a course of a telephonic conversation about ndia’s moves in the semicon space.

After that conversation, I was wondering how quickly semicon technology had started to move. How quickly, from a has-been all these years, India was suddenly emerging as a semicon base to reckon with. How quickly, the geometry had moved from 90nm to, now, 22nm!

Dr Dutta also added that there would be more emphasis in India on doing high-end designs. In fact, whether it is frequency, number of gates, high complexity, etc., all of those would be driven by applications. India is now ready for doing high-end complex designs.

Indian companies are now definitely excelling in the design services sector. Some of them have also grown significantly. It is believed that they have also taken a load off the international design services company. Some of these Indian companies are now also developing their own IPs — a paradigm shift in itself!

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